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preliminary publication# 22235 rev: i amendment/0 issue date: april 2001 refer to amd?s website (www.amd.com) for the latest information. am79c874 netphy?-1lp low power 10/100-tx/fx ethernet transceiver distinctive characteristics 10/100base-tx ethernet phy device with 100base-fx fiber optic support typical power consumption of 0.3 w sends/receives data reliably over cable lengths greater than 130 meters mii mode supports 100base-x and 10base-t 7-wire (general purpose serial interface (gpsi)) mode supports 10base-t three powerwise ? management modes (from 300 mw typical) ? power down : only management responds typical power = 3 mw ? unplugged : no cable, no receive clock typical power = 100 mw ? idle wire : no wire signal, no receiver power typical power = 285 mw; mac saves over 100 mw supports 1:1 or 1.25:1 transmit transformer ? using a 1.25:1 ratio saves 20% transmit power consumption ? no external filters or chokes required waveshaping ? no external filter required full and half-duplex operation with full-featured auto-negotiation function led indicators: link, tx activity, rx activity, collision, 10 mbps, 100 mbps, full or half duplex mdio/mdc operates up to 25 mhz automatic polarity detection built-in loopback and test modes single 3.3-v power supply with 5-v i/o tolerance 12 mm x 12 mm 80-pin tqfp package support for industrial temperature (-40 c to +85 c) general description the am79c874 netphy-1lp device provides the phys- ical (phy) layer and transceiver functions for one 10/100 mbps ethernet port. it delivers the dual benefits of cmos low power consumption and small package size. operating at 3.3 v, it consumes only 0.3 w. three power management modes provide options for even lower power consumption levels. the small 12x12 mm 80-pin pql package conserves valuable board space on adapter cards, switch uplinks, and embedded ether- net applications. the netphy-1lp 10/100 mbps ethernet phy device is ieee 802.3 compliant. it can receive and transmit data reliably at over 130 meters. it includes on-chip input fil- tering and output waveshaping for unshielded twisted pair operation without requiring external filters or chokes. the netphy-1lp device can use 1:1 isolation transformers or 1.25:1 isolation transformers. 1.25:1 isolation transformers provide 20% lower transmit power consumption. a pecl interface is available for 100base-fx applications. interface to the media access controller (mac) layer is established via the standard media independent inter- face (mii), a 5-bit symbol interface, or a 7-wire (gpsi) interface. auto-negotiation determines the network speed and full or half-duplex operation. automatic po- larity correction is performed during auto-negotiation and during 10base-t signal reception. multiple led pins are provided for front panel status feedback. one option is to use two bi-color leds to show when the device is in 100base-tx or 10base-t mode (by illuminating), half or full duplex (by the color), and when data is being received (by blinking). individual leds can indicate link detection, collision detection, and data being transmitted. the netphy-1lp device needs only one external 25- mhz oscillator or crystal because it uses a dual-speed clock synthesizer to generate all other required clock domains. the receiver has an adaptive equalizer/dc restoration circuit for accurate clock/data recovery from the 100base-tx signal. the netphy-1lp device is available in the commercial (0c to +70c) or industrial (-40c to +85c) tempera- ture ranges. the industrial temperature range is well suited to environments, such as enclosures with re- stricted air flow or outdoor equipment.
2 am79c874 preliminary block diagram mac mii data interface mdc/mdio phyad[4:0] pcs framer carrier detect 4b/5b tp_pmd mlt-3 blw stream cipher 25 mhz 25 mhz 10tx 10rx 20 mhz xtl+ xtl- clk test led drivers 100tx 100rx tx+ tx- rx+ rx- transformer interface mux pma clock recovery link monitor signal detect mii serial management interface and registers pll clk generator test led control auto- negotiation 10base-t control/status rx flp 22235i-1
am79c874 3 preliminary connection diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 am79c874 netphy-1lp pcsbp isodef iso tgnd1 refclk clk25 burn_in rst pwrdn pllvcc pllgnd ognd1 ovdd1 phyad[4]/10rxd- phyad[3]/10rxd+ phyad[2]/10txd++ phyad[1]/10txd+ phyad[0]/10txd- gpio[0]/10txd--/7wire gpio[1]/tp125 eqvcc adpvcc leddpx/ledtxb ledspd[1]/ledtxa/clk25en anega tech_sel[0] tech_sel[1] tech_sel[2] crvvcc crvgnd ognd2 ovdd2 ledlnk/led_10lnk/led_pcsbp_sd ledtx/ledbtb ledrx/ledsel ledcol/scram_en ledspd[0]/ledbta/fx_sel intr crs/10crs col/10col mdio mdc rxd[3] rxd[2] rxd[1] rxd[0]/10rxd vdd1 dgnd1 rx_dv rx_clk/10rxclk rx_er/rxd[4] tx_er/txd[4] tx_clk/10txclk/pcsbp_clk tx_en/10txen dgnd2 vdd2 txd[0]/10txd txd[1] txd[2] txd[3] tvcc2 tvcc1 tx- tx+ tgnd2 xtl+ xtl- refvcc ibref refgnd fxt- fxt+ test2 test1/fxr+ test0/fxr- eqgnd rx+ rx- test3/sdi+ rptr 22235i-2
4 am79c874 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. device number/description am79c874 netphy-1lp low power 10/100-tx/fx ethernet tr a n s c e i ve r temperature range c = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) alternate packaging option not applicable package type v = 80-pin thin plastic quad flat pack (pqt 80) am79c874 v speed option not applicable c/i valid combinations am79c874 vc am79c874 vi
am79c874 5 preliminary related amd products part no. description controllers am79c90 cmos local area network controller for ethernet (c-lance ? ) integrated controllers am79c940 media access controller for ethernet (mace ? ) am79c961a pcnet ? -isa ii full duplex single-chip ethernet controller for isa bus am79c965a pcnet ? -32 single-chip 32-bit ethernet controller for 486 and vl buses am79c970a pcnet ? -pci ii full duplex single-chip ethernet controller for pci local bus am79c973/ am79c975 pcnet ? - fast iii single-chip 10/100 mbps pci ethernet controller with integrated phy am79c976 pcnet ? -pro 10/100 mbps pci ethernet pci controller am79c978 pcnet ? -home single-chip 1/10 mbps pci home networking controller physical layer devices (single-port) am79c901 homephy ? single-chip 1/10 mbps home networking phy physical layer devices (multi-port) am79c875 netphy ? -4lp low power quad10/100-tx/fx ethernet transceiver integrated repeater/hub devices am79c984a enhanced integrated multiport repeater (eimr ? ) am79c985 enhanced integrated multiport repeater plus (eimr+ ? )
6 am79c874 preliminary table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 standard products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 related amd products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 media connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 mii/7-wire (gpsi) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 miscellaneous functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 led port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 functional description15 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 mii mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 7-wire (gpsi) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5b symbol mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 100base-x block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4b/5b encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 scrambler/descrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 link monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 mlt-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 adaptive equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 baseline wander compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 clock/data recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 pll clock synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 10base-t block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 twisted pair transmit process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 twisted pair receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 twisted pair interface status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 collision detect function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 jabber function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 reverse polarity detection and correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 auto-negotiation and miscellaneous functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 parallel detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 far-end fault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 sqe (heartbeat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 led port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 power savings mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 selectable transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 unplugged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 idle wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 phy control and management block (pcm block) . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 register administration for 100base-x phy device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 description of the methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 bad management frame handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
am79c874 7 preliminary register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 serial management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 mii management control register (register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 mii management status register (register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 phy identifier 1 register (register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 phy identifier 2 register (register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 auto-negotiation advertisement register (register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 auto-negotiation link partner ability register in base page format (register 5) . . . . . . . . 33 auto-negotiation link partner ability register in next page format (register 5) . . . . . . . . .33 auto-negotiation expansion register (register 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 auto-negotiation next page advertisement register (register 7) . . . . . . . . . . . . . . . . . . . . 35 reserved registers (registers 8-15, 20, 22, 25-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 miscellaneous features register (register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 interrupt control/status register (register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 diagnostic register (register 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 power/loopback register (register 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 mode control register (register 21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 disconnect counter register (register 23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 receive error counter register (register 24). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 commercial (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 industrial (i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 dc characteristics41 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 6 system clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 mlt-3 signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 mii management signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 mii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 100 mbps mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 100 mbps mii receive timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 mbps mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 mbps mii receive timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 gpsi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 10 mbps gpsi receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 10 mbps gpsi receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 10 mbps gpsi collision timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 10 mbps gpsi transmit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 10 mbps gpsi transmit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 pqt80 (measured in millimeters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 list of figures figure 1.fxt and fxr termination for 100base-fx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 2.mlt-3 waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 3.tx and rx termination for 100base-tx and 10base-t. . . . . . . . . . . . . . . . . . . . . 21 figure 5.standard led configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 6.advanced led configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 7.phy management read and write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 8.mlt-3 receive input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 9.mlt-3 and 10base-t test load with 1:1 transformer ratio. . . . . . . . . . . . . . . . . . . . . 44 figure 10.mlt-3 and 10base-t test load with 1.25:1 transformer ratio . . . . . . . . . . . . . . . . . 44 figure 11.near-end 100base-tx waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 12.10base-t waveform with 1:1 transformer ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8 am79c874 preliminary figure 13.pecl test loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 14.clock signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 15.mlt-3 test waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 16.management bus transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17.management bus receive timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 18.100 mbps mii transmit start of packet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 19.100 mbps transmit end of packet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 20.100 mbps mii receive start of packet timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 21.100 mbps mii receive end of packet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 22.10 mbps mii transmit start of packet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 23.10 mbps mii transmit end of packet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 24.10 mbps mii receive start of packet timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 25.10 mbps mii receive end of packet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 26.gpsi receive timing - start of reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 27.gpsi receive timing - end of reception (last bit = 0) . . . . . . . . . . . . . . . . . . . . . . . 56 figure 28.gpsi receive timing - end of reception (last bit = 1) . . . . . . . . . . . . . . . . . . . . . . . 57 figure 29.gpsi collision timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 30.gpsi transmit timing - start of transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 31.gpsi transmit 10txclk and 10txd timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 32.test load for 10rxd, 10crs, 10rxclk, 10txclk and 10col . . . . . . . . . . . . . . . . 58 list of tables table 1.mii pins that relate to 10 mbps 7-wire (gpsi) mode . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 2.code-group mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 3.speed and duplex capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4 table 4.standard led selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 5.advanced led selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6.clause 22 management frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 7.phy address setting frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 8.register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 9.legend for register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 10.mii management control register (register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 11.mii management status register (register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 12.phy identifier 1 register (register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 13.phy identifier 2 register (register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 14.auto-negotiation advertisement register (register 4) . . . . . . . . . . . . . . . . . . . . . . . . .32 table 15.auto-negotiation link partner ability register in base page format (register 5) . . . .33 table 16.auto-negotiation link partner ability register in next page format (register 5) . . . . .33 table 17.auto-negotiation expansion register (register 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 18.auto-negotiation next page advertisement register (register 7) . . . . . . . . . . . . . . . .35 table 19.miscellaneous features register (register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 20.interrupt control/status register (register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 21.diagnostic register (register 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 22.power/loopback register (register 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 23.mode control register (register 21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 24.disconnect counter (register 23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 25.receive error counter register (register 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
am79c874 9 preliminary pin designations listed by pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 pcsbp 21 mdio 41 col/10col 61 rptr 2 isodef 22 mdc 42 crs/10crs 62 test3/sdi+ 3 iso 23 rxd[3] 43 intr 63 rx- 4 tgnd1 24 rxd[2] 44 ledspd[0] / ledbta/fx_sel 64 rx+ 5 refclk 25 rxd[1] 45 ledcol / scram_en 65 eqgnd 6 clk25 26 rxd[0]/10rxd 46 ledrx /ledsel 66 test0/fxr- 7 burn_in 27 vdd1 47 ledtx /ledbtb 67 test1/fxr+ 8rst 28 dgnd1 48 ledlnk / led_10lnk/ led_pcsbp_sd 68 test2 9 pwrdn 29 rx_dv 49 ovdd2 69 fxt+ 10 pllvcc 30 rx_clk/10rxclk 50 ognd2 70 fxt- 11 pllgnd 31 rx_er/rxd[4] 51 crvgnd 71 refgnd 12 ognd1 32 tx_er/txd[4] 52 crvvcc 72 ibref 13 ovdd1 33 tx_clk/10txclk/ pcsbp_clk 53 tech_sel[2] 73 refvcc 14 phyad[4]/10rxd- 34 tx_en/10txen 54 tech_sel[1] 74 xtl- 15 phyad[3]/10rxd+ 35 dgnd2 55 tech_sel[0] 75 xtl+ 16 phyad[2]/10txd++ 36 vdd2 56 anega 76 tgnd2 17 phyad[1]/10txd+ 37 txd[0]/10txd 57 ledspd[1] / ledtxa/clk25en 77 tx+ 18 phyad[0]/10txd- 38 txd[1] 58 leddpx /ledtxb 78 tx- 19 gpio[0]/10txd--/ 7wire 39 txd[2] 59 adpvcc 79 tvcc1 20 gpio[1]/tp125 40 txd[3] 60 eqvcc 80 tvcc2
10 am79c874 preliminary pin descriptions the following table describes terms used in the pin de- scriptions. media connections tx transmitter outputs analog output the tx pins are the differential transmit output pair. the tx pins transmit 10base-t or mlt-3 signals de- pending on the state of the link of the port. rx receiver input analog input the rx pins are the differential receive input pair. the rx pins can receive 10base-t or mlt-3 signals de- pending on the state of the link of the port. fxt fx transmit analog output these pins are not connected in 10/100base-tx mode. when fx_sel (pin 44) is pulled low, these pins be- come the ecl level transmit output for 100base-fx. test0/fxr- test output/fx receive -analog output/input when burn_in (pin 7) is pulled high, this pin serves as a test mode output monitor pin. when fx_sel (pin 44) is pulled low, this pin becomes an ecl level negative receive input for 100base-fx. this pin can be left unconnected when the device is op- erating in 100base-tx or 10base-t mode. test1/fxr+ test output/fx receive +analog output/input when burn_in (pin 7) is pulled high, this pin serves as a test mode output monitor pin. when fx_sel (pin 44) is pulled low, this pin becomes an ecl level positive receive input for 100base-fx. this pin can be left unconnected when the device is op- erating in 100base-tx or 10base-t mode. test3/sdi+ fx transceiver signal detect analog output/input when burn_in (pin 7) is pulled high, this pin serves as a test mode output monitor pin. this pin is not connected in 10/100base-tx mode. when fx_sel (pin 44) is pulled low, this pin becomes the signal detect input from the fiber-optic trans- ceiver. when the signal quality is good, the sdi+ pin should be driven high. mii/7-wire (gpsi) signals rxd[3:0] mii receive data output, high impedance the data is synchronous with rx_clk when rx_dv is active. when the 7-wire 10base-t interface operation is enabled (gpio[0]= high), rxd[0] will serve as the 10 mhz serial data output. rx_dv receive data valid output, high impedance rx_dv is asserted when the netphy-1lp device is presenting recovered nibbles on rxd[3:0]. this in- cludes the preamble through the last nibble of the data stream on rxd[3:0]. in 100base-x mode, the /j/k/ is considered part of the preamble; thus rx_dv is as- serted when /j/k/ is detected. in 10base-t mode, rx_dv is asserted (and data is presented on rxd[3:0]) when the device detects valid preamble bits. rx_dv is synchronized to rx_clk. rx_clk/10rxclk receive clock output, high impedance a continuous clock (which is active while link is estab- lished) provides the timing reference for rx_dv, rx_er, and rxd[3:0] signals. it is 25 mhz in 100base-tx/fx and 2.5 mhz in 10base-t. to further reduce power consumption of the overall system, the device provides an optional mode enabled through mii register 16, bit 0 in which rx_clk is held inactive (low) when no data is received. if rx_clk is needed when link is not established, the netphy-1lp must be placed into digital loopback or force the link via register 21, bits 13 or 14. when 7-wire 10base-t mode is enabled, this pin will provide a 10 mhz clock. rx_clk is high impedance when the iso pin is enabled rx_er/rxd[4] receive error output, high impedance when rx_er is active high, it indicates an error has been detected during frame reception. this pin becomes the highest-order bit of the receive 5- bit code group in pcs bypass (pcsbp=high) mode. this output is ignored in 10base-t operation. term description input digital input to the phy analog input analog input to the phy output digital output from the phy analog output analog output from the phy high impedance tri-state capable output from the phy pull-up phy has internal pull-up resistor. nc=high pull-down phy has internal pull-down resistor. nc=low
am79c874 11 preliminary tx_er/txd[4] transmit error input when tx_er is asserted, it will cause the 4b/5b en- coding process to substitute the transmit error code- group /h/ for the encoded data word. this pin becomes the higher-order bit of the transmit 5- bit code group in pcs bypass (pcsbp=high) mode. this input is ignored in the 10base-t operation. tx_clk/10txclk/pcsbpclk transmit clock output, high impedance a free-running clock which provides timing reference for tx_en, tx_er, and txd[3:0] signals. it is 25 mhz in 100base-tx/fx and 2.5 mhz in 10base-t. when 7-wire gpsi mode is enabled, this pin will pro- vide a 10 mhz transmit clock for 10base-t operation. when the cable is unplugged, the 10txclk ceases operation. when working in pcsbp mode, this pin will provide a 25 mhz clock for 100base-tx operation, and 20 mhz clock for 10base-t operation. tx_clk is high imped- ance when the iso pin is enabled. tx_en/10txen transmit enable input the tx_en pin is asserted by the mac to indicate that data is present on txd[3:0]. when 7-wire 10base-t mode is enabled, this pin is the transmit enable signal. txd[3:1] transmit data input the mac will source txd[3:1] to the phy. the data will be synchronous with tx_clk when tx_en is as- serted. the phy will clock in the data based on the ris- ing edge of tx_clk. txd[0]/10txd transmit data[0]/10 mbps transmit data input the mac will source txd[0] to the phy. the data will be synchronous with tx_clk when tx_en is as- serted. the phy will clock in the data based on the ris- ing edge tx_clk. when 7-wire 10base-t mode is enabled, this pin will transmit serial data. col/10col collision output, high impedance col is asserted high when a collision is detected on the media. col is also used for the sqe test function in 10base-t mode. 10col is asserted high when a collision is detected during 7-wire interface mode. crs/10crs carrier sense output, high impedance crs is asserted high when twisted pair media is non- idle. this signal is used for both 10base-t and 100base-x. in full duplex mode, crs responds only to rx activity. in half duplex mode, crs responds to both rx and tx activity. 10crs is used as the carrier sense output for the 7-wire interface mode. miscellaneous functions pcsbp pcs bypass input, pull-down the 100base-tx pcs as well as scrambler/descram- bler will be bypassed when pcsbp is pulled high via a 10 k resistor. tx_er will become txd[4] and rx_er will become rxd[4]. in 10 mbps pcs bypass mode, the mii signals are not valid. the signals that interface to the mac (i.e., decpc 21143) are located on pins 14 to 19. the sig- nals are defined as follows: ? 10rxd are the differential receive outputs to the mac. ? 10txd are the differential transmit inputs from the mac. ? 10txd++/10txd-- are the differential pre- emphasis transmit outputs from the mac. when left unconnected, the device operates in mii or gpsi mode. isodef isolate default input, pull-down this pin is used when multiple phys are connected to a single mac. when it is pulled high via a 10 k resis- tor, the mii interface will be high impedance. the status of this pin will be latched into mii register 0, bit 10 after reset. when this pin is left unconnected, the default condition of the mii output pins are not in the high impedance state. iso isolate input, pull-down the mii output pins will become high impedance when iso is pulled high via a 10 k resistor. however, the mii input pins will still respond to data. this allows multiple phys to be attached to the same mii interface. the same isolate condition can also be achieved by assert- ing mii register 0, bit 10. in repeater mode, iso will not tri-state the crs pin. when this pin is left unconnected, the mii output pins are not in the high impedance state.
12 am79c874 preliminary refclk clock input input, pull-down this pin connects to a 25-mhz + 50 ppm clock source with a 40% to 60% duty cycle. when a crystal input is used, this pin should be pulled low via a 1 k resistor. xtl crystal inputs analog input these pins should be connected to a 25-mhz crystal. the crystal should be parallel resonant and have a fre- quency stability of + 100 ppm and a frequency tolerance of + 50 ppm. refclk (pin 5) should be pulled low when the crystal is used as a clock source. these pins may be left unconnected when refclk is used as a clock source. clk25 25 mhz clock output when the clk25en pin is pulled low, the clk25 pin provides a continuous 25 mhz clock to the mac. burn_in test enable input, pull-down when pulled high via a 10 k resistor, this pin forces the netphy-1lp device into burn-in mode for reliability assurance control. when left unconnected the device operates normally. test2 test output analog output when burn_in (pin 7) is pulled high, this pin serves as a test mode output monitor pin. test2 can be left unconnected when the device is operating. rst reset input, pull-up a low input forces the netphy-1lp device to a known reset state. the chip can also be reset through internal power-on-reset or mii register 0, bit 15. pwrdn power down input, pull-down if this pin is pulled high via a 10 k resistor on the rising edge of reset, the device will power down the analog modules and reset the digital circuits. however, the de- vice will still respond to mdc/mdio data. the same power-down state can also be achieved through the mii register 0, bit 11. however, the device will respond ac- tivity on the pwrdn pin even when bit 11 is not set. when left unconnected, the device operates normally. phyad[4:0] phy address input/output, pull-up these pins allow 32 configurable phy addresses. the phyad will also determine the scramble seed, which helps to reduce emi when there are multiple ports switching at the same time (repeater/switch applica- tions). each pin should either be pulled low via a 1 k 4.7 k resistor (set bit to zero) or left unconnected (set bit to 1) in order to achieve the desired phy ad- dress. new address changes take effect after a reset has been issued, or at power up. in pcs bypass mode, phyad[4:0] and gpio[1:0] serves as 10base-t serial input and output. note: in gpsi mode, the phyad pins must be set to addresses other than 00h. gpio[0]/10txd--/7wire general purpose i/o 0 input/output, pull-up if this pin is pulled low via a 10 k resistor, on the rising edge of reset, the device will operate in 10base-t 7-wire (gpsi) mode. if this pin is left unconnected dur- ing the rising edge of reset, the device will operate in standard mii mode. after the reset operation has completed, this pin can function as an input or an output (dependent on the value of gpio[0] dir (mii register 16, bit 6). if mii register 16, bit 6 is set high, gpio[0] is an input. the input value on the gpio[0] pin will be reflected in mii register 16, bit 7 ? gpio[0] data. if mii register 16, bit 6 is set low, gpio[0] is an output. the value of mii register 16, bit 7 will be reflected on the gpio[0] output pin. gpio[1]/tp125 general purpose i/o 1 input/output, pull-down if this pin is pulled high via a 10 k resistor, on the ris- ing edge of reset, the device will be enabled for use with a 1.25:1 transmit ratio transformer. if this pin is left unconnected during the rising edge of reset, the device will be enabled for use with a 1:1 transmit ratio transformer. after the reset operation has completed, this pin can function as an input or an output (dependent on the value of gpio[1] dir ? mii register 16, bit 8). if mii register 16, bit 8 is set high, gpio[1] is an input. the input value on the gpio[1] pin will be reflected in mii register 16, bit 9 ? gpio[1] data. if mii register 16, bit 8 is set low, gpio[1] is an output. the value of mii register 16, bit 9 will be reflected on the gpio[1] output pin. mdio management data input/output pull-down this pin is a bidirectional data interface used by the mac to access management registers within the net- phy-1lp device. this pin has an internal pull-down, therefore, it requires a 1.5 k pull-up resistor as speci- fied in ieee 802.3 when interfaced with a mac. this pin can be left unconnected when management is not used.
am79c874 13 preliminary mdc management data clock input this clock is sourced by the mac and is used to synchronize mdio data. when management is not used, this pin should be tied to ground. intr interrupt output, high impedance this pin is used to signal an interrupt to the mac. the pin will be forced high or low (normally high impedance) to signal an interrupt depending upon the value of the intr_levl bit, mii register 16, bit 14. the events which trigger an interrupt can be programmed via the interrupt control register (register 17). tech_sel[2:0] technology select input, pull-up the technology select pins, in conjunction with the anega pin, set the speed and duplex configurations for the device on the rising edge of reset. these capa- bilities are reflected in mii register 1 and mii register 4. table 3 lists the possible configurations for the de- vice. if the input is listed as low, the pin should be pulled to ground via a 10 k resistor on the rising edge of reset. if the input is listed as high, the pin can be left unconnected. note: by using resistors to hard wire the tech_sel[2:0] pins and the anega pin, using the mdc/mdio management interface pins becomes op- tional. the device?s speed, duplex, and auto-negotia- tion capabilities are set via hardware. if the management interface is used, the registers cannot be set to a higher capability than the hard-wired setting. the highest capabilities are full duplex, 100 mbps, and auto-negotiation enabled. anega auto-negotiation ability input, pull-up when this pin is pulled to ground via a 10 k resistor, on the rising edge of reset, auto-negotiation is dis- abled. when this pin is left unconnected, on the rising edge of reset, auto-negotiation is enabled. note that this pin acts in conjunction with tech_sel[2:0] on the rising edge of reset. refer to table 3 to determine the desired configuration for the device. note: by using resistors to hard wire the tech_sel[2:0] pins and the anega pin, using the mdc/mdio management interface pins becomes op- tional. the device?s speed, duplex, and auto-negotia- tion capabilities are set via hardware. if the management interface is used, the registers cannot be set to a higher capability than the hard-wired setting. the highest capabilities are full duplex, 100 mbps, and auto-negotiation enabled. rptr repeater mode input this pin should be tied to ground via a 10 k resistor if repeater mode is to be disabled. when this pin is pulled high via a 10 k resistor, repeater mode will be en- abled. repeater mode can also enabled via mii regis- ter 16, bit 15. led port pins ledrx /led_sel receive led/led configuration select input/output, pull-up when this pin is pulled low via a 5 k resistor, on the rising edge of reset, the advanced led configuration is enabled. if there is no pull-down resistor present, on the rising edge of reset, the standard led configuration is enabled. after the rising edge of reset this pin controls the re- ceive led. this pin toggles between high and low when data is received. when the device is operating in the standard led mode, refer to table 4 and figure 5 in the led port configuration section. when the device is op- erating in the advanced led mode, refer to table 5 and figure 6 in the led port configuration section. ledcol /scram_en collision led/scrambler enable input/output, pull-up when this pin is pulled low via a 1-k resistor, on the rising edge of reset, the scrambler/descrambler is dis- abled. if no pull-down resistor is present, on the rising edge of reset, the scrambler/descrambler is enabled. after the rising edge of reset this pin controls the colli- sion led. this pin toggles between high and low when there is a collision in half-duplex operation. in full- duplex operation this pin is inactive. when the device is operating in the standard led mode (see ledrx /led- sel pin description), refer to table 4 and figure 5 in the led port configuration section. when the device is op- erating in the advanced led mode (see ledrx /led- sel pin description), see table 5 and figure 6. ledlnk /led_10lnk/led_pcsbp_sd link led/7-wire link led/pcsbp signal detect output when a link is established in 100base-x or 10base-t mode, this pin will assume a logic low level. when a link is established in 7-wire mode, this pin will assume a logic high level. when in pcs bypass mode, this pin assumes a logic high level indicating signal detect. refer to table 4 and figure 4 in the led port configu- ration section if the device is operating in the standard led mode. see table 5 and figure 5 if the device is op- erating in the advanced led mode.
14 am79c874 preliminary note: if 7-wire mode is chosen the polarity of the led should be reversed and the cathode of the led should be tied to ground. ledspd[0] /ledbta/fx_sel 100 mbps speed led/advanced led/fiber select input/output, pull-up when this pin is pulled low via a 1 k resistor, on the rising edge of reset, the device will be enabled for 100base-fx operation. when no pull-down resistor is present, on the rising edge of reset, the device will be enabled for 100base-tx or 10base-t operation. when the standard led configuration is enabled (see ledrx /ledsel pin description), this pin serves as the 100 mbps speed led. a logic low level indicates 100 mbps operation. a logic high level indicates 10 mbps operation. refer to table 4 and figure 5 in the led port configuration section to determine the correct polarity of the led. when the advanced led configuration is enabled, this pin works in conjunction with ledtx /ledbtb (pin 47). refer to table 5 and figure 6 in the led port configu- ration section to determine the correct polarity of the bi- directional led. ledtx /ledbtb transmit led/advanced led output when the standard led configuration is enabled (see ledrx /ledsel pin description), this pin serves as the transmit led. this pin toggles between high and low when data is transmitted. refer to table 4 and figure 5 in the led port configuration section to determine the correct polarity of the led. when the advanced led configuration is enabled, this pin works in conjunction with ledspd[0] /ledbta/ fx_sel (pin 44). refer to table 5 and figure 6 in the led port configuration section to determine the cor- rect polarity of the bi-directional led. ledspd[1] /ledtxa/clk25en 10 mbps speed led/advanced led/25 mhz clock enable input/output, pull-up when this pin is pulled low via a 1 k resistor, on the rising edge of reset, the device will output a 25 mhz clock on clk25 (pin 6). when no pull-down resistor is present, on the rising edge of reset, clk25 is inactive. when the standard led configuration is enabled (see ledrx /ledsel pin description), this pin serves as the 10 mbps speed led. a logic low level indicates 10 mbps operation. a logic high level indicates 100 mbps operation. refer to table 4 and figure 5 in the led port configuration section to determine the correct polarity of the led. when the advanced led configuration is enabled, this pin works in conjunction with leddpx /ledtxb (pin 58). refer to table 5 and figure 6 in the led port con- figuration section to determine the correct polarity of the bi-directional led. leddpx /ledtxb duplex led/advanced led output when the standard led configuration is enabled (see ledrx /ledsel description), this pin serves as the duplex led. a logic low level indicates full duplex oper- ation. a logic high level indicates half duplex operation. see table 4 and figure 5 in the led port configuration section to determine the correct polarity of the led. when the advanced led configuration is enabled, this pin works in conjunction with ledspd[1] ledtxa/ clk25en (pin 57). refer to table 5 and figure 6 in the led port configuration section to determine the cor- rect polarity of the bi-directional led. bias ibref reference bias resistor analog this pin must be tied to an external 10.0 k (1%) resis- tor which should be connected to ground. the 1% re- sistor provides the bandgap reference voltage. power and ground pllvcc, ovdd1, ovdd2, vdd1, vdd2, crvvcc, adpvcc, eqvcc, refvcc, tvcc1, tvcc2 power pins power these pins are 3.3 v power for sections of the netphy-1lp device as follows: pllvcc is power for the pll; ovdd1 and ovdd2 are power for the i/o; vdd1 and vdd2 are power for the digital logic; crvvcc is power for clock recovery; ad- pvcc and eqvcc are power for the equalizer; refvcc is power for the bandgap reference; and tvcc1 and tvcc2 are power for the transmit driver. pllgnd, ognd1, ognd2, dgnd1, dgnd2, crvgnd, eqgnd, refgnd, tgnd1, tgnd2 ground pins power these pins are ground for the power pins as follows: pllgnd is ground for pllvcc; ognd is ground for ovdd; dgnd is ground for vdd; crvgnd is ground for crvvcc and adpvcc; eqgnd is ground for eqvcc; refgnd is ground for refvcc; and tgnd is ground for tvcc. note: bypass capacitors of 0.1 f between the power and ground pins are recommended. the four areas where the capacitors must be very close to the pins (within 3 mm) are the pll (pins 10 and 11), clock re- covery (pins 51 and 52), equalizer (pins 60 and 65), and bandgap reference (pins 71 and 73) areas. the other bypass capacitors should be placed as close to the pins as possible.
am79c874 15 preliminary functional description the netphy-1lp device integrates the 100base-x pcs, pma, and pmd functions and the 10base-t manchester endec and transceiver functions in a sin- gle chip for ethernet 10 mbps and 100 mbps opera- tions. it performs 4b/5b, mlt3, nrzi, and manchester encoding and decoding, clock and data recovery, stream cipher scrambling/descrambling, adaptive equalization, line transmission, carrier sense and link integrity monitor, auto-negotiation, and mii manage- ment functions. it provides an ieee 802.3u compatible media independent interface (mii) to communicate with an ethernet media access controller (mac). se- lection of 10 mbps or 100 mbps operation is based on settings of internal serial management interface regis- ters or determined by the on-chip auto-negotiation logic. the device can be set to operate either in full-du- plex mode or half-duplex mode for either 10 mbps or 100 mbps. the netphy-1lp device communicates with a re- peater, switch, or mac device through either the media independent interface (mii) or the 10 mbps 7-wire (gpsi) interface. the netphy-1lp device consists of the following func- tional blocks: mii mode 7-wire (gpsi) mode pcs bypass (5b symbol) mode 100base-x block including: ? transmit process ? receive process ? 4b/5b encoder and decoder ? scrambler and descrambler ? link monitor ? mlt-3 ? adaptive equalizer ? baseline wander compensation ? clock/data recovery ? pll clock synthesizer 10base-t block including: ? transmit process ? receive process ? interface status ? collision detect ? jabber ? reverse polarity detection and correction auto-negotiation and miscellaneous functions in- cluding: ? auto-negotiation ? parallel detection ? far-end fault ? sqe (heartbeat) ? loopback operation ? reset led port configuration power savings mechanisms including: ? selectable transformer ? power down ? unplugged ? idle wire phy control and management modes of operation the mii/gpsi/5b symbol interface provides the data path connection between the netphy-1lp transceiver and the media access controller (mac), repeater, or switch. the mdc and mdio pins are responsible for communication between the netphy-1lp transceiver and the station management entity (sta). the mdc and mdio pins can be used in any mode of operation. mii mode the purpose of the mii mode is to provide a simple, easy to implement connection between the mac rec- onciliation layer and the phy. the mii is designed to make the differences between various media transpar- ent to the mac sublayer. the mii consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to fa- cilitate data transfers between the phy and the recon- ciliation layer. txd (transmit data) is a nibble (4 bits) of data that are driven by the reconciliation sublayer synchro- nously with respect to tx_clk. for each tx_clk period which tx_en is asserted, txd[3:0] are ac- cepted for transmission by the phy. tx_clk (transmit clock) output to the mac recon- ciliation sublayer is a continuous clock that provides the timing reference for the transfer of the tx_en, txd, and tx_er signals. tx_en (transmit enable) input from the mac recon- ciliation sublayer to indicate nibbles are being presented on the mii for transmission on the physi- cal medium. tx_er (transmit coding error) transi- tions synchronously with respect to tx_clk. if tx_er is asserted for one or more clock periods, and tx_en is asserted, the phy will emit one or more symbols that are not part of the valid data de- limiter set somewhere in the frame being transmit- ted.
16 am79c874 preliminary rxd (receive data) is a nibble (4 bits) of data that is sampled by the reconciliation sublayer synchro- nously with respect to rx_clk. for each rx_clk period which rx_dv is asserted, rxd[3:0] are transferred from the phy to the mac reconciliation sublayer. rx_clk (receive clock) output to the mac reconcil- iation sublayer is a continuous clock (during link only) that provides the timing reference for the transfer of the rx_dv, rxd, and rx_er signals. rx_dv (receive data valid) input from the phy to in- dicate the phy is presenting recovered and de- coded nibbles to the mac reconciliation sublayer. to interpret a receive frame correctly by the recon- ciliation sublayer, rx_dv must encompass the frame starting no later than the start-of-frame de- limiter and excluding any end-stream delimiter. rx_er (receive error) transitions synchronously with respect to rx_clk. rx_er will be asserted for 1 or more clock periods to indicate to the recon- ciliation sublayer that an error was detected some- where in the frame being received by the phy. crs (carrier sense) is asserted by the phy when either the transmit or receive medium is non-idle and deasserted by the phy when the transmit and receive medium are idle. 7-wire (gpsi) mode 7-wire (gpsi) mode uses the existing mii pins, but data is transferred only on txd[0] and rxd[0]. this mode is used in a general purpose serial interface (gpsi) configuration for 10base-t. if the gpio[0] pin is low at the rising edge of reset, then gpsi mode is selected. for this configuration, tx_clk runs at 10 mhz. when the cable is unplugged, 10txclk ceases operation. the mii pins that relate to 7-wire (gpsi) mode are shown in table 1. the unused input pins in this mode should be tied to ground through a 1 k resistor. the rptr pin must be connected to gnd. table 1. mii pins that relate to 10 mbps 7-wire (gpsi) mode note: crs ends one and one-half bit times after the last data bit. the effect is one or two dribbling bits on every packet. all macs truncate packets to eliminate the dribbling bits. the only noticeable effect is that all crc errors are recorded as framing errors. use the tech_sel[2:0] to select the desired 10base- t operation. for example, to auto-negotiate between full duplex and half duplex at 10 mbps, set aneg=1 and tech[2:0]=101. 5b symbol mode the purpose of the 5b symbol mode is to provide a way for the mac to do the 4b/5b encoding/decoding and scrambling/descrambling in 100 mbps operation. this is useful in mac similar to the intel/dec 21143 mac. in 10 mbps operation, the mii signals are not used. in- stead, the netphy-1lp device operates as a 10base-t transceiver, providing received data to the mac over a serial differential pair (see pin descrip- tions, pcsbp pin). the mac uses two serial differential pairs to provide transmit data to the netphy-1lp de- vice, where the two differential pairs are combined in the netphy-1lp device to compensate for inter-symbol interference on the twisted pair medium. 100base-x block the functions performed by the device include encod- ing of mii 4-bit data (4b/5b), decoding of received code groups (5b/4b), generating carrier sense and collision detect indications, serialization of code groups for transmission, de-serialization of serial data upon re- ception, mapping of transmit, receive, carrier sense, and collision at the mii interface, and recovery of clock from the incoming data stream. it offers stream cipher scrambling and descrambling capability for 100base- tx applications. in the transmit data path for 100 mbps, the netphy-1lp transceiver receives 4-bit (nibble) wide data across the mii at 25 million nibbles per second. for 100base-tx applications, it encodes and scram- bles the data, serializes it, and transmits an mlt-3 data stream to the media via an isolation transformer. for 100base-fx applications, it encodes and serializes the data and transmits a pseudo-ecl (pecl) data stream to the fiber optic transmitter. see figure 1. in the receive data path for 100 mbps, the netphy-1lp transceiver receives an mlt-3 data stream from the network. for 100base-tx, it then recovers the clock from the data stream, de-serializes the data stream, and descrambles/decodes the data stream (5b/4b) be- fore presenting it at the mii interface. mii pin name 7-wire (gpsi) tx_clk/10txclk transmit clock txd[0]/10txd transmit serial data stream txd[3:1] not used tx_en/10txen transmit enable tx_er not used rx_clk/10rxclk receive clock rxd[0] /10rxd receive serial data stream rxd[3:1] not used col/10col collision detect rx_er not used crs/10crs carrier sense detect mii pin name 7-wire (gpsi)
am79c874 17 preliminary figure 1. fxt and fxr termination for 100base-fx for 100base-fx operation, the netphy-1lp device receives a pecl data stream from the fiber optic trans- ceiver and decodes that data stream. the 100base-x block consists of the following sub- blocks: ? transmit process ? receive process ? 4b/5b encoder and decoder ? scrambler/descrambler ? link monitor ? far end fault generation and detection & code- group generator ? mlt-3 encoder/decoder with adaptive equalization ? baseline restoration ? clock recovery transmit process the transmit process generates code-groups based on the transmit control and data signals on the mii. this process is also responsible for frame encapsulation into a physical layer stream, generating the collision signal based on whether a carrier is received simulta- neously during transmission and generating the carrier sense crs and collision col signals at the mii. the transmit process is implemented in compliance with the transmit state diagram as defined in clause 24 of the ieee 802.3u specification. the netphy-1lp device transmit function converts synchronous 4-bit data nibbles from the mii to a 125- mbps differential serial data stream. the entire opera- tion is synchronous to a 25-mhz clock and a 125-mhz clock. both clocks are generated by an on-chip pll clock synthesizer that is locked to an external 25-mhz clock source. in 100base-fx mode, the netphy-1lp device will by- pass the scrambler. the output data is an nrzi pecl signal. this pecl level signal will then drive the fiber transmitter. receive process the receive path includes a receiver with adaptive equalization and dc restoration, mlt-3-to-nrzi con- version, data and clock recovery at 125-mhz, nrzi-to- nrz conversion, serial-to-parallel conversion, de- scrambling, and 5b to 4b decoding. the receiver circuit starts with a dc bias for the differential rx inputs, fol- lows with a low-pass filter to filter out high-frequency noise from the transmission channel media. an energy detect circuit is also added to determine whether there is any signal energy on the media. this is useful in the power-saving mode. (see the description in power hfbr/hfct-5903 am79c874 netphy-1lp 5 rd+ 4 rd- 3 sd+ 10 td- 9 td+ 3.3 v mt-rj 1 k ? 69 ? 69 ? 3.3 v 3.3 v 183 ? 183 ? 183 ? 183 ? 130 ? 130 ? 130 ? 0.1 f 0.1 f test1/fxr+ test0/fxr- test3/sdi+ fxt- fxt+ fx_sel 69 ? 69 ? 22235i-3
18 am79c874 preliminary savings mechanisms section). all of the amplification ratio and slicer thresholds are set by the on-chip band- gap reference. in 100base-fx mode, signal will be received through a pecl receiver, and directly passed to the clock re- covery for data/clock extraction. in fx mode, the scrambler/descrambler cipher will be bypassed. 4b/5b encoder/decoder the 100 mbps process in the netphy-1lp device uses the 4b/5b encoding scheme as defined in ieee 802.3, section 24. this scheme converts between raw data on the mii and encoded data on the media pins. the en- coder converts raw data to the 4b/5b code. it also in- serts the stream boundary delimiters (/j/k/ and /t/r/) at the beginning and end of the data stream as appro- priate. the decoder converts between encoded data on the media pins and raw data on the mii. it also de- tects the stream boundary delimiters to help determine the start and end of packets. the code-group mapping is defined in table 2. the 4b/5b encoding is bypassed when mii register 21, bit 1 is set to ? 1 ? , or the pcsbp pin (pin 1) is strapped high. scrambler/descrambler the 4b/5b encoded data has repetitive patterns which result in peaks in the rf spectrum large enough to keep the system from meeting the standards set by regulatory agencies such as the fcc. the peaks in the radiated signal are reduced significantly by scrambling the transmitted signal. scramblers add the output of a random generator to the data signal. the resulting sig- nal has fewer repetitive data patterns. after reset, the scrambler seed in each port will be set to the phy address value to help improve the emi per- formance of the device. the scrambled data stream is descrambled at the re- ceiver by adding it to the output of another random gen- erator. the receiver ? s random generator uses the same function as the transmitter ? s random generator. in 100base-tx mode, all 5-bit transmit data streams are scrambled as defined by the tp-pmd stream cipher function in order to reduce radiated emissions on the twisted pair cable. the scrambler encodes a plain text nrz bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function: x[n] = x[n-11] + x[n-9] (modulo 2) the scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range, thus eliminating peaks at a single fre- quency. when mii register 21, bit 2 is set to ? 1, ? the data scrambling function is disabled and the 5-bit data stream is clocked directly to the device ? s pma sublayer. l ink monitor signal levels are detected through a squelch detection circuit. a signal detect (sd) circuit following the equal- izer is asserted high whenever the peak detector senses a post-equalized signal with a peak-to-ground voltage level larger than 400 mv. this is approximately 40 percent of the normal signal voltage level. in addi- tion, the energy level must be sustained longer than 2 ms in order for the signal detect to be asserted. it gets de-asserted approximately 1 ms after the energy level is consistently less than 300 mv from peak-to-ground. the link signal is forced to low during a local loopback operation (i.e., when mii register 0, bit 14, loopback is asserted) and forced to high when a remote loopback is taking place (i.e., when mii register 21, bit 3, en_rpbk, is set). in 100base-tx mode, when no signal or an invalid sig- nal is detected on the receive pair, the link monitor will enter in the ? link fail ? state where only the scrambled idle code will be transmitted. when a valid signal is de- tected for a minimum period of time, the link monitor will then enter the link pass state when transmit and re- ceive functions are entered. in 100base-fx mode, the external fiber-optic receiver performs the signal energy detection function and com- municates this information directly to the netphy-1lp device through the sdi+ pin.
am79c874 19 preliminary table 2. code-group mapping mii (txd[3:0]) name pcs code-group interpretation 0 0 0 0 0 1 1 1 1 0 data 0 0 0 0 1 1 0 1 0 0 1 data 1 0 0 1 0 2 1 0 1 0 0 data 2 0 0 1 1 3 1 0 1 0 1 data 3 0 1 0 0 4 0 1 0 1 0 data 4 0 1 0 1 5 0 1 0 1 1 data 5 0 1 10 6 0 1 1 1 0 data 6 0 1 1 1 7 0 1 1 1 1 data 7 1 0 0 0 8 1 0 0 1 0 data 8 1 0 0 1 9 1 0 0 1 1 data 9 1 0 1 0 a 1 0 1 1 0 data a 1 0 1 1 b 1 0 1 1 1 data b 1 1 0 0 c 1 1 0 1 0 data c 1 1 0 1 d 1 1 0 1 1 data d 1 1 1 0 e 1 1 1 0 0 data e 1 1 1 1 f 1 1 1 0 1 data f undefined i 1 1 1 1 1 idle; used as inter-stream fill code 0 1 0 1 j 1 1 0 0 0 start-of-stream delimiter, part 1 of 2; always used in pairs with k 0 1 0 1 k 1 0 0 0 1 start-of-stream delimiter, part 2 of 2; always used in pairs with j undefined t 0 1 1 0 1 end-of-stream delimiter, part 1 of 2; always used in pairs with r undefined r 0 0 1 1 1 end-of-stream delimiter, part 2 of 2; always used in pairs with t undefined h 0 0 1 0 0 transmit error; used to force signaling errors undefined v 0 0 0 0 0 invalid code undefined v 0 0 0 0 1 invalid code undefined v 0 0 0 1 0 invalid code undefined v 0 0 0 1 1 invalid code undefined v 0 0 1 0 1 invalid code undefined v 0 0 1 1 0 invalid code undefined v 0 1 0 0 0 invalid code undefined v 0 1 1 0 0 invalid code undefined v 1 0 0 0 0 invalid code undefined v 1 1 0 0 1 invalid code
20 am79c874 preliminary mlt-3 this block is responsible for converting the nrzi data stream from the pdx block to the mlt-3 encoded data stream. the effect of mlt-3 is the reduction of energy on the copper media (tx or fx cable) in the critical fre- quency range of 1 mhz to 100 mhz. the receive sec- tion of this block is responsible for equalizing and amplifying the received data stream and link detection. the adaptive equalizer compensates for the amplitude and phase distortion due to the cable. mlt-3 is a tri-level signal. all transitions are between 0 v and +1 v or 0 v and -1 v. a transition has a logical value of 1 and a lack of a transition has a logical value of 0. the benefit of mlt-3 is that it reduces the maxi- mum frequency over the data line. the bit rate of tx data is 125 mbps. the maximum frequency (using nrzi) is half of 62.5 mhz. mlt-3 reduces the maximum frequency to 31.25 mhz. a data signal stream following mlt-3 rules is illustrated in figure 2. the data stream is 1010101. figure 2. mlt-3 waveform the tx drivers convert the nrzi serial output to mlt-3 format. the rx receivers convert the received mlt-3 signals to nrzi. the transmit and receive sig- nals will be compliant with ieee 802.3u, section 25. the required signals (mlt-3) are described in detail in ansi x3.263:1995 tp-pmd revision 2.2 (1995). the netphy-1lp device provides on-chip filtering. ex- ternal filters are not required for either the transmit or receive signals. the traces from the transformer to the netphy-1lp device should have a controlled imped- ance as a differential pair of 100 ohms. the same is true between the transformer and the rj-45 connector. the tx pins can be connected to the media via either a 1:1 transformer or a 1.25:1 transformer. the 1.25:1 ratio provides a 20% transmit power savings over the 1:1 ratio. refer to figure 3. adaptive equalizer the netphy-1lp device is designed to accommodate a maximum cable length of 140 meters utp cat-5 ca- ble. 140 meters of utp cat-5 cable has an attenuation of 31 db at 100 mhz. the typical attenuation of a 100 meter cable is 21 db. the worst case attenuation is around 24-26 db defined by tp-pmd. the amplitude and phase distortion from the cable will cause intersymbol interference (isi) which makes clock and data recovery impossible. the adaptive equalizer is made by closely matching the inverse transfer func- tion of the twist-pair cable. this is a variable equalizer that changes its equalizer frequency response in ac- cordance to cable length. the cable length is estimated based on comparisons of incoming signal strength against some of the known cable characteristics. the equalizer has a monotonical frequency response, and tunes itself automatically for any cable length to com- pensate for the amplitude and phase distortion incurred from the cable. baseline wander compensation the 100base-tx data stream is not always dc bal- anced. the transformer blocks the dc component of the incoming signal, thus the dc offset of the differen- tial receive inputs can wander. the shift in the signal levels, coupled with non-zero rise and fall times of the serial stream can cause pulse-width distortion. this creates jitter and a possible increase in error rates. therefore, a dc restoration circuit is needed to com- pensate for the attenuation of the dc component. the netphy-1lp device implements a patent- pending dc restoration circuit. unlike the traditional im- plementation, it does not need the feedback informa- tion from the slicer and clock recovery circuit. this not only simplifies the system/circuit design, but also elim- inates any random/systematic offset on the receive path. in 10base-t and 100base-fx modes, the base- line wander correction circuit is not required and there- fore will be bypassed. mlt-3 1010101 8 ns 22235i-4
am79c874 21 preliminary figure 3. tx and rx termination for 100base-tx and 10base-t clock/data recovery the equalized mlt-3 signal passes through a slicer cir- cuit which then converts it to nrzi format. the net- phy-1lp device uses an analog phase-locked loop (apll) to extract clock information from the incoming nrzi data. the extracted clock is used to re-time the data stream and set the data boundaries. the transmit clock is locked to the 25-mhz clock input, while the re- ceive clock is locked to the incoming data streams. when initial lock is achieved, the apll switches to lock to the data stream, extracts a 125 mhz clock from it and use that for bit framing to recover data. the recovered 125 mhz clock is also used to generate the 25 mhz rx_clk. the apll requires no external components for its operation and has high noise immunity and low jitter. it provides fast phase align (lock) to data in one transition and its data/clock acquisition time after power-on is less than 60 transitions. the apll can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. when no valid data is present, i.e., when the sd is de-asserted, the apll switches back to lock with tx_clk, thus pro- viding a continuously running rx_clk. the recovered data is converted from nrzi-to-nrz and then to a 5-bit parallel format. the 5-bit parallel data is not necessarily aligned to 4b/5b code-group ? s symbol boundary. the data is presented to pcs at re- ceive data register output, gated by the 25-mhz rx_clk. pll clock synthesizer the netphy-1lp device includes an on-chip pll clock synthesizer that generates a 125 mhz and a 25 mhz clock for the 100base-tx or a 100 mhz and 20 mhz clock for the 10base-t and auto-negotiation opera- tions. only one external 25 mhz crystal or a signal source is required as a reference clock. after power-on or reset, the pll clock synthesizer is defaulted to generating the 20 mhz clock output and will stay active until the 100base-x operation mode is selected. rx+ tx+ rx- tx- 0.1 f 0.1 f v dd (note 1) (note 1) 470 pf, 2 kv (chassis ground) (8) (7) tx+ (1) (5) (4) tx- (2) rx+ (3) rx- (6) 75 ? 75 ? 75 ? 75 ? isolation transformer with common-mode chokes rj45 connector 1:1 or 1.25:1 1:1 0.1 f (note 2) (note 2) 22235i-5 notes: 1. 49.9 if a 1:1 isolation transformer is used or 78.1 if a 1.25:1 isolation transformer is used. 2. 49.9 is normal, but 54.9 can be used for extended cable length operation.
22 am79c874 preliminary 10base-t block the netphy-1lp transceiver incorporates the 10base-t physical layer functions, including clock re- covery (endec), maus, and transceiver functions. the netphy-1lp transceiver receives 10-mbps data from the mac, switch, or repeater across the mii at 2.5 million nibbles per second (parallel), or 10 million bits per second (serial). it then manchester encodes the data before transmission to the network. refer to figure 4 for the 10base-t transmit and re- ceive data paths. figure 4. 10base-t transmit /receive data paths twisted pair transmit process in 10base-t mode, manchester code will be gener- ated by the 10base-t core logic, which will then be synthesized through the output waveshaping driver. this will help reduce any emi emission, eliminating the need for an external filter. data transmission over the 10base-t medium requires use of the integrated 10base-t mau and uses the differential driver cir- cuitry on the tx pins. tx is a differential twisted-pair driver. when properly terminated, tx meets the transmitter electrical re- quirements for 10base-t transmitters as specified in ieee 802.3, section 14.3.1.2. the load is a twisted pair cable that meets ieee 802.3, section 14.4. the tx signal is filtered on the chip to reduce har- monic content per section 14.3.2.1 (10base-t). since filtering is performed in silicon, tx can be connected directly to a standard transformer. external filtering modules are not needed twisted pair receive process in 10base-t mode, the signal first passes through a third order elliptical filter, which filters all the noise from the cable, board, and transformer. this eliminates the need for a 10base-t external filter. a manchester de- coder and a serial-to-parallel converter then follow to generate the 4-bit nibble in mii mode. rx+ ports are differential twisted-pair receivers. when properly terminated, each rx+ port meets the electri- cal requirements for 10base-t receivers as specified in ieee 802.3, section 14.3.1.3. each receiver has in- ternal filtering and does not require external filter mod- ules or common mode chokes. signals appearing at the rx differential input pair are routed to the internal decoder. the receiver function meets the propagation delays and jitter requirements specified by the 10base-t standard. the receiver squelch level drops to half its threshold value after un- squelch to allow reception of minimum amplitude sig- nals and to mitigate carrier fade in the event of worst case signal attenuation and crosstalk noise conditions. twisted pair interface status the netphy-1lp transceiver will power up in the link fail state. the auto-negotiation algorithm will apply to allow it to enter the link pass state. a link-pulse detec- tion circuit constantly monitors the rx pins for the presence of valid link pulses. in the link pass state, re- ceive activity which passes the pulse width/amplitude requirements of the rx inputs cause the pcs control block to assert carrier sense (crs) signal at the mii interface. collision detect function simultaneous activity (presence of valid data signals) from both the internal encoder transmit function and the twisted pair rx pins constitutes a collision, thereby causing the pcs control block to assert the col pin at the mii. collisions cause the pcs control block to assert the carrier sense (crs) and collision (col) signals at the mii. in the link fail state, this block would cause the pcs control block to de-assert carrier sense (crs) and collision (col). jabber function the jabber function inhibits the 10base-t twisted pair transmit function of the netphy-1lp transceiver device if the tx circuits are active for an excessive period (20-150 ms). this prevents one port from disrupting the network due to a stuck-on or faulty transmitter condi- tion. if the maximum transmit time is exceeded, the data path through the 10base-t transmitter circuitry is disabled (although link test pulses will continue to be clock data manchester encoder clock data manchester decoder squelch circuit rx driver rx tx tx driver loopback (register 0) 22235i-6
am79c874 23 preliminary sent). the pcs control block also asserts the col pin at the mii and sets the jabber detect bit in mii register 1. once the internal transmit data stream from the mendec stops, an unjab time of 250-750 ms will elapse before this block causes the pcs control block to de-assert the col indication and re-enable the transmit circuitry. when jabber is detected, this block causes the pcs control block to assert the col pin and allows the pcs control block to assert or de-assert the crs pin to in- dicate the current state of the rx pair. if there is no re- ceive activity on rx, this block causes the pcs control block to assert only the col pin at the mii. if there is rx activity, this block causes the pcs control block to assert both col and crs at the mii. the jab- ber function can be disabled by setting mii register 21, bit 12. reverse polarity detection and correction proper 10base-t receiver operation requires that the differential input signal be the correct polarity. that is, the rx+ line is connected to the rx+ input pin, and the rx- line is connected to the rx- input pin. improper setup of the external wiring can cause the polarity to be reversed. the netphy-1lp receiver has the ability to detect the polarity of the incoming signal and compen- sate for it. thus, the proper signal will appear on the mdi regardless of the polarity of the input signals. the internal polarity detection and correction circuitry is set during the reception of the normal link pulses (nlp) or packets. the receiver detects the polarity of the input signal on the first nlp. it locks the polarity cor- rection circuitry after the reception of two consecutive packets. the state of the polarity correction circuitry is locked as long as link is established. auto-negotiation and miscellaneous functions auto-negotiation the netphy-1lp device has the ability to negotiate its mode of operation over the twisted pair using the auto- negotiation mechanism defined in clause 28 of the ieee 802.3u specification. auto-negotiation may be enabled or disabled by hardware (anega, pin 56) or software (mii register 0, bit 12) control (see table 3). the netphy-1lp device will automatically choose its mode of operation by advertising its abilities and com- paring them with those received from its link partner whenever auto-negotiation is enabled. the content of mii register 4 is sent to the link partner during auto-negotiation, coded in fast link pulses (flps). mii register 4, bits 8:5 reflect the state of the tech_sel[2:0] pins after reset. after reset, software can change any of these bits from 1 to 0 and back to 1, but not from 0 to 1 via the man- agement interface. therefore, hardware settings have priority over software. a write to register 4 does not cause the device to restart auto-negotiation. when auto-negotiation is enabled, the netphy-1lp device sends flp during the one of the following con- ditions: (a) power on, (b) link loss, or (c) restart com- mand. at the same time, the device monitors incoming data to determine its mode of operation. when the de- vice receives a burst of flps from its link partner with three identical link code words (ignoring acknowledge bit), it stores these code words in mii register 5 and waits for the next three identical code words. once the device detects the second code word, it will configure itself to the highest technology that is common to both ends. the technology priorities are: (1) 100base-tx, full-duplex, (2) 100base-tx, half-duplex, (3) 10base- t, full-duplex, and (4) 10base-t half-duplex. parallel detection the parallel detection circuit is enabled as soon as ei- ther 10base-t idle or 100base-tx idle is detected. the mode of operation gets configured based on the technology of the incoming signal. the netphy-1lp device can also check for a 10base-t nlp or 100base-tx idle symbol. if either is detected, the de- vice automatically configures to match the detected op- erating speed in half-duplex mode. this ability allows the device to communicate with legacy 10base-t and 100base-tx systems.
24 am79c874 preliminary table 3. speed and duplex capabilities notes: 1. mii register 0 (speed and duplex bits) must be set by the mac to achieve a link. 2. the advertised abilities in mii register 4 cannot exceed the abilities of mii register 1. auto-negotiation should always rema in enabled. 3. when auto-negotiation is enabled, these bits can be written but will be ignored by the phy. far-end fault auto-negotiation provides a remote fault capability for detecting asymmetric link failure. since 100base-fx systems do not use auto-negotiation, an alternative, in-band signaling scheme, far-end fault is used to sig- nal remote fault conditions. far-end fault is a stream of 63 consecutive 1s followed by one logic 0. this pattern is repeated three times. a far-end fault will be sig- naled under three conditions: (1) when no activity is re- ceived from the link partner, (2) when the clock recovery circuit detects signal error or pll lock error, and (3) when the management entity sets the transmit fef bit (mii register 21, bit 7). the far-end fault mechanism defaults to enable 100base-fx mode and disable 100base-tx and 10base-t modes, and may be controlled by software after reset. sqe (heartbeat) when the sqe test is enabled, a col signal with a 5- 15 bit time pulse will be issued after each transmitting packet. sqe is enabled and disabled via mii register 16, bit 11. loopback operation a local loopback and remote loopback are provided for testing. they can be enabled by writing to either mii register 0, bit 14 (loopback) or mii register 21, bit 3 (en_rpbk). the local loopback routes transmitted data at the out- put of nrz-to-nrzi conversion module back to the receiving path ? s clock and data recovery module for connection to pcs in 5 bits symbol format. this loop- back is used to check all the connections at the 5-bit symbol bus side and the operation of analog phase locked loop. in local loopback, the sd output is forced to logic one and tx outputs are tristated. during local loopback, a 10-mbps link is sent to the link partner. in either 100base-tx or 10base-t loopback mode, the link for 10 mbps is forced (register 21, bit 14) and is seen externally. if packets are transmitted from the device under test (dut), the link between the dut and link partner is lost. ceasing transmission causes the link to go back up. in remote loopback, incoming data passes through the equalizer and clock recovery, then loop back to nrzi/ mlt3 conversion module and out to the driver. this loopback is used to check the device ? s connection on the media side and the operation of its internal adaptive equalizer, phase-locked loop, and digital wave shape synthesizer. during remote loopback, signal detect (sd) output is forced to logic zero. note that remote loopback operates only in 100base-tx mode. anega tech[2] tech[1] tech[0] speed duplex aneg-en capabilities/aneg (hardwired on board) (changeable in mii register 0) 0 0 0 0 yes (note 1) yes (note 1) no all capabilities 0 0 0 1 no no no 10hd 0 0 1 0 no no no 100hd 0 0 1 1 no no no 100hd 0 1 0 0 yes (note 1) yes (note 1) no all capabilities 0 1 0 1 no no no 10fd 0 1 1 0 no no no 100fd 0 1 1 1 no no no 100fd 1 0 0 0 yes (note 3) yes (note 3) yes (note 2) no capabilities, aneg 1 0 0 1 yes (note 3) yes (note 3) yes (note 2) 10hd, aneg 1 0 1 0 yes (note 3) yes (note 3) yes (note 2) 100hd, aneg 1 0 1 1 yes (note 3) yes (note 3) yes (note 2) 100hd, 10hd, aneg 1 1 0 0 yes (note 3) yes (note 3) yes (note 2) no capabilities, aneg 1 1 0 1 yes (note 3) yes (note 3) yes (note 2) 10fd/hd, aneg 1 1 1 0 yes (note 3) yes (note 3) yes (note 2) 100fd/hd, aneg 1 1 1 1 yes (note 2) yes (note 3) yes (note 2) all capabilities, aneg
am79c874 25 preliminary external loopback can be accomplished using an ex- ternal loopback cable with tx connected to rx. ex- ternal loopback works for both 10 mbps and 100 mbps after setting register 0, bit 8 to force full duplex and bit 13 to set the speed. reset the netphy-1lp device can be reset in the three fol- lowing ways: 1. during initial power on (with internal power on reset circuit). 2. at hardware reset. a logic low signal of 10 ms pulse width applied to the rst pin. 3. at software reset. write a 1 to mii register 0, bit 15. led port configuration the netphy-1lp device has several pins that are used for both device configuration and led drivers. these pins set the configuration of the device on the rising edge of rst and thereafter indicate the state of the re- spective port. see table 4 for standard led selections and table 5 for advanced led selections. the polarity of the led drivers (active-low or active- high) is set at the rising edge of rst . if the pin is low at the rising edge of rst , it becomes an active-high driver. if it is high at the rising edge of rst , it becomes an active-low driver. proper configuration requires pull-up or pull-down re- sistors. as shown in the pin description sections, each of the led/configuration pins has internal pull-up re- sistors. if the pin ? s led functionality is not used, the pin may still need to be terminated via an external pull- down resistor according to the desired configuration. the resistor value is not critical and can be in the range of 1 k to 10 k . if the corresponding led is used, the terminating resistor must be placed in parallel with the led. suggested led connection diagrams simplifying the board design are shown in figure 5 (standard) and figure 6 (advanced). the value of the series resistor (r l ) should be selected to ensure sufficient illumination of the led. it is depen- dent on the rating of the led. table 4. standard led selections notes: 1. 1 means on (logic level low since active low). 2. 0 means off (logic level high since active low). 3. t means toggles (will end at logic level high). mode ledsdp[0] ledsdp[1] ledlnk leddpx ledtx ledrx ledcol no link 0 0 0 0 0 0 0 10hd-rx 0 1 1 0 0 t 0 10hd-tx 0 1 1 0 t 0 0 10hd-col 0 1 1 0 t t t 10fd-rx 0 1 1 1 0 t 0 10fd-tx 0 1 1 1 t 0 0 10fd-rx+tx 0 1 1 1 t t 0 100hd-rx 1 0 1 0 0 t 0 100hd-tx 1 0 1 0 t 0 0 100hd-col 1 0 1 0 t t t 100fd-rx 1 0 1 1 0 t 0 100fd-tx 1 0 1 1 t 0 0 100fd-rx+tx 1 0 1 1 t t 0
26 am79c874 preliminary figure 5. standard led configuration table 5. advanced led selections notes: 1. led flashes for rx and tx activity. 2. led flashes for rx activity. 3. 0 means logic level low at the pin. 4. 1 means logic level high at the pin. mode ledbtx/ ledbta (pin 44) ledtx/ ledbtb (pin 47) ledbt/ ledtxa (pin 57) ledfdx/ ledtxb (pin 58) no link 0 0 0 0 10bt half duplex 1 0 0 0 10bt half activity flash (note 1) 0 0 0 10bt full duplex 0 1 0 0 10bt full activity 0 flash (note 2) 0 0 100bt half duplex 0 0 1 0 100bt half activity 0 0 flash (note 1) 0 100bt full duplex 0 0 0 1 100bt full activity 0 0 0 flash (note 2) 330 vcc 100 mbps ledspd[0] 10 mbps ledsp[1] collision ledcol duplex leddpx transmit ledtx receive ledrx link (note 1) ledlnk link (note 2) ledlnk led 330 vcc led 330 vcc led 330 vcc led 330 vcc led 330 vcc led 330 vcc led 330 led 22235i-7 notes : 1. use for non 7-wire interface configurations. 2. use for 7-wire interface configurations.
am79c874 27 preliminary figure 6. advanced led configuration power savings mechanisms the power consumption of the device is significantly re- duced by its built-in power down features. separate power supply lines are also used to power the 10base-t circuitry and the 100base-tx circuitry. therefore, the two modes of operation can be turned- on and turned-off independently. whenever the net- phy-1lp device is set to operate in a 100base-tx mode, the 10base-t circuitry is powered down, and when in 10base-t mode, the 100base-tx circuitry is powered down. the netphy-1lp device offers the following power management: selectable transformer, power down, unplugged, and idle. selectable transformer the tx outputs can drive either a 1:1 transformer or a 1.25:1 transformer. the latter can be used to reduce transmit power further. the current at the tx pins for a 1:1 ratio transformer is 40 ma for mlt-3 and 100 ma for 10base-t. using the 1.25:1 ratio reduces the cur- rent to 30 ma for mlt-3 and 67 ma for 10base-t. the cost of using the 1.25:1 option is in impedance coupling. the reflected capacitance is increased by the square of the ratio (1.25 2 = 1.56). thus, the reflected capacitance on the media side is roughly one and a half times the capacitance on the board. extra care in the layout to control capacitance on the board is required. power down most of the netphy-1lp device can be disabled via the power down bit in mii register 0, bit 11. setting this bit will power down the entire device with the exception of the mdio/mdc management circuitry. unplugged the tx output driver limits the drive capability if the re- ceiver does not detect a link partner within 4 seconds. this prevents ? wasted ? power. if the receiver detects the absence of a link partner, the transmitter is limited to transmitting normal link pulses. any energy detected by the receiver enables full transmit and receive capa- bilities. the power savings is most notable when the port is unconnected. typical power drops to one third of normal. idle wire this can be achieved by writing to mii register 16, bit 0. during this mode, if there is no data other than idles coming in, the receive clock (rx_clk) will turn off to save power for the attached controller. rx_clk will re- sume operation one clock period prior to the assertion of rx_dv. the receive clock will again shut off 64 clock cycles after rx_dv gets deasserted. typical power savings of 100 mw can be realized in some macs. ledbta ledbtb 10base-t led indicator ledtxa ledtxb 100base-tx led indicator 300 5 k 330 330 330 330 300 dual-color led dual-color led vcc receive ledrx collision ledcol link (note 1) ledlnk link (note 2) ledlnk vcc vcc led led led led 22235i-8 notes : 1. use for non 7-wire interface configurations. 2. use for 7-wire interface configurations.
28 am79c874 preliminary phy control and management block (pcm block) register administration for 100base-x phy device the management interface specified in clause 22 of the ieee 802.3u standard provides for a simple two wire, serial interface to connect a management entity and a managed phy for the purpose of controlling the phy and gathering status information. the two lines are management data input/output (mdio), and man- agement data clock (mdc). a station management entity which is attached to multiple phy entities must have prior knowledge of the appropriate phy address for each phy entity. description of the methodology the management interface physically transports man- agement information across the mii. the information is encapsulated in a frame format as specified in clause 22 of ieee 802.3u draft standard and is shown in ta b l e 6 . table 6. clause 22 management frame format the phyad field, which is five bits wide, allows 32 unique phy addresses. the managed phy layer de- vice that is connected to a station management entity via the mii interface has to respond to transactions addressed to the phy address. a station management entity attached to multiple phys, such as in a managed 802.3 repeater or ethernet switch, is required to have prior knowledge of the appropriate phy address. see table 7 and figure 7. table 7. phy address setting frame structure figure 7. phy management read and write operations pre st op phyad regadd ta data idle read 1.1 01 10 aaaaa rrrrr z0 d...........d z write 1.1 01 01 aaaaa rrrrr 10 d...........d z pre st op phyad regadd ta data idle read 1.1 01 10 00000 rrrrr z0 xxxxxxxxxppaaaaa z write 1.1 01 01 00000 rrrrr 10 xxxxxxxxxppaaaaa z idle start opcode (read) phy address 16h, port 2 register address mii status, 1h ta register data idle z z z mdc mdio (phy) mdio (sta) z z 01101011000001 00110000 01000001 0 z z read operation idle start opcode (write) phy address 16h, port 2 register address mii control, 0h ta register data idle z z mdc mdio (sta) z 0101101100000010011000 100000000 0 z write operation 22235i-9
am79c874 29 preliminary bad management frame handling the management block of the device can recognize management frames without preambles (preamble suppression). however, if it receives a bad manage- ment frame, it will go into a bad management frame state. it will stay in this state and will not respond to any management frame without preambles until a frame with a full 32-bit preamble is received, then it will return to normal operation. a bad management frame is a frame that does not comply with the ieee standard specification. it can be one with less than 32-bit preamble, with illegal op field, etc. however, a frame with more than 32 preamble bits is considered to be a good frame. after a reset, the netphy-1lp device requires a mini- mum preamble of 32 bits before management data (mdio) can be received. after that, the management data being received by the netphy-1lp device does not require a preamble. register descriptions the following registers given in table 8 are supported (register addresses are in decimal). table 8. register summary the physical address of the phy is set using the pins defined as phyad[4:0]. these input signals are strapped externally and sampled as when reset goes high. the phyad pins can be reprogrammed via soft- ware. serial management registers a detailed definition of each serial management regis- ter follows. the mode legend is shown in table 9. table 9. legend for register table register address (in decimal) description 0 mii management control register 1 mii management status register 2 phy identifier 1 register 3 phy identifier 2 register 4 auto-negotiation advertisement register 5 auto-negotiation link partner ability register 6 auto-negotiation expansion register 7 next page advertisement register 8-15 reserved 16 miscellaneous features register 17 interrupt control/status register 18 diagnostic register 19 power management & loopback register 20 reserved 21 mode control register 22 reserved 23 disconnect counter 24 receive error counter 25-31 reserved type description rw readable and writable sc self clearing ll latch low until clear ro read only rc cleared on the read operation lh latch high until clear
30 am79c874 preliminary mii management control register (register 0) table 10. mii management control register (register 0) reg bit name description read/ write default 0 15 reset 1 = phy reset. 0 = normal operation. this bit is self-clearing. rw/sc 0 0 14 loopback 1 = enable loopback mode. this will loopback txd to rxd, thus it will ignore all the activity on the cable media. during loopback, a 10-mbps link is sent to the link partner (register 21, bit 14 is forced.) 0 = disable loopback mode. normal operation. rw 0 0 13 speed select 1 = 100 mbps, 0 = 10 mbps. this bit will be ignored if auto negotiation is enabled (0.12 = 1). refer to table 3 to determine when this bit can be changed. rw set by tech[2:0] pins 012 auto-neg enable 1 = enable auto-negotiate process (overrides 0.13 and 0.8). 0 = disable auto-negotiate process. mode selection is controlled via bit 0.8, 0.13 or through tech[2:0] pins. refer to table 3 to determine when this bit can be changed. rw set by anega pin 011power down 1 = power down. the netphy-1lp device will shut off all blocks except for mdio/mdc interface. setting pwrdn pin to high will achieve the same result. 0 = normal operation. rw 0 010isolate 1 = electrically isolate the phy from mii. however, phy is still able to respond to mdc/mdio. the default value of this bit depends on isodef pin, i.e., isodef=1, iso bit will set to 1, & isodef=0, iso bit will set to 0. 0 = normal operation. rw set by isodef pin 09 restart auto- negotiation 1 = restart auto-negotiation process. 0 = normal operation. rw/sc 0 0 8 duplex mode 1 = full duplex, 0 = half duplex. refer to table 3 to determine when this bit can be changed. rw set by tech[2:0] pins 0 7 collision test 1 = enable collision test, which issues the col signal in response to the assertion of tx_en signal. collision test is disabled if pcsbp pin is high. collision test is enabled regardless of the duplex mode. 0 = disable col test. rw 0 0 6:0 reserved write as 0, ignore when read. rw 0
am79c874 31 preliminary mii management status register (register 1) table 11. mii management status register (register 1) phy identifier 1 register (register 2) table 12. phy identifier 1 register (register 2) reg bit name description read/ write default 1 15 100base-t4 1 = 100base-t4 able. 0 = not 100base-t4 able. ro 0 114 100base-tx full duplex 1 = 100base-tx full duplex. 0 = no 100base-tx full duplex ability. ro set by tech[2:0] pins 113 100base-tx half duplex 1 = 100base-tx half duplex. 0 = no tx half-duplex ability. ro set by tech[2:0] pins 112 10base-t full duplex 1 = 10base-t full duplex. 0 = no 10base-t full duplex ability. ro set by tech[2:0] pins 111 10base-t half duplex 1 = 10base-t half duplex. 0 = no 10base-t ability. ro set by tech[2:0] pins 1 10:7 reserved ignore when read. ro 0 1 6 management frame preamble suppression the device accepts management frames that do not have a preamble after receiving a management frame with a 32-bit or longer preamble. ro 1 15 auto-negotiation complete 1 = auto-negotiation process completed. registers 4, 5, and 6 are valid after this bit is set. 0 = auto-negotiation process not completed. ro 0 1 4 remote fault 1 = remote fault condition detected. 0 = no remote fault. this bit will remain set until it is read via the management interface. ro/lh 0 13 auto-negotiation ability 1 = able to perform auto-negotiation function; value is determined by anega pin. 0 = unable to perform auto-negotiation function. ro set by anega pin 1 2 link status 1 = link is established; however, if the netphy-1lp device link fails, this bit will be cleared and remain cleared until register 1 is read via management interface. 0 = link is down. ro/ll 0 1 1 jabber detect 1 = jabber condition detected. 0 = no jabber condition detected. ro/lh 0 10 extended capability 1 = extended register capable. this bit is tied permanently to one. ro 1 reg name description read/ write default 215oui composed of the 3rd through 18th bits of the organizationally unique identifier (oui), respectively. ro 0022(h)
32 am79c874 preliminary phy identifier 2 register (register 3) table 13. phy identifier 2 register (register 3) auto-negotiation advertisement register (register 4) table 14. auto-negotiation advertisement register (register 4) reg bit name description read/ write default 3 15:10 oui assigned to the 19th through 24th bits of the oui. ro 010101 3 9:4 model number six-bit manufacturer ? s model number. ro 100001 3 3:0 revision number four-bit manufacturer ? s revision number. ro 1011 reg bit name description read/ write default 415next page 1 = next page enabled. 0 = next page disabled. rw 0 4 14 acknowledge this bit will be set internally after receiving three consecutive and consistent flp bursts. ro 0 4 13 remote fault 1 = remote fault supported. 0 = no remote fault. rw 0 4 12:11 reserved for future technology. rw 0 410fdfc full duplex flow control: 1 = advertise that the dte(mac) has implemented both the optional mac control sublayer and the pause function as specified in clause 31 and annex 31 b of 802.3u. 0 = no mac-based full duplex flow control. rw 0 4 9 100base-t4 netphy-1lp device does not support 100base-t4 function, i.e., this bit ties to zero. ro 0 48 100base-tx full duplex 1 = 100base-tx full duplex. 0 = no 100base-tx full duplex ability. default is set by register 1.14. rw set by tech [2:0] pins 47 100base-tx half duplex 1 = 100base-tx half duplex. 0 = no 100base-tx half duplex capability. default is set by register 1.13 rw set by tech[2:0] pins 46 10base-t full duplex 1 = 10 mbps full duplex. 0 = no 10 mbps full duplex capability. default is set by register 1.12. rw set by tech[2:0] pins 45 10base-t half duplex 1 = 10 mbps half duplex. 0 = no 10 mbps half duplex capability default is set by register 1.11. rw set by tech[2:0] pins 4 4:0 selector field [00001] = ieee 802.3. ro 00001
am79c874 33 preliminary auto-negotiation link partner ability register in base page format (register 5) table 15. auto-negotiation link partner ability register in base page format (register 5) auto-negotiation link partner ability register in next page format (register 5) table 16. auto-negotiation link partner ability register in next page format (register 5) reg bit name description read/ write default 515next page 1 = next page requested by link partner 0 = next page not requested ro 0 5 14 acknowledge 1 = link partner acknowledgement 0 = no link partner acknowledgement ro 0 5 13 remote fault 1 = link partner remote fault request 0 = no link partner remote fault request ro 0 5 12:11 reserved reserved for future technology ro 5 10 flow control 1 = link partner supports flow control. 0 = link partner does not support flow control. ro 0 5 9 100base-t4 1 = remote partner is 100base-t4 capable 0 = remote partner is not 100base-t4 capable ro 0 58 100base-tx full duplex 1 = link partner is capable of 100base-tx full duplex 0 = link partner is not capable of 100base-tx full duplex ro 0 57 100base-tx half duplex 1 = link partner is capable of 100base-tx half duplex 0 = link partner is not capable of 100base-tx half duplex ro 0 56 10base-t full duplex 1 = link partner is capable of 10base-t full duplex 0 = link partner is not capable of 10base-t full duplex ro 0 55 10base-t half duplex 1 = link partner is capable of 10base-t half duplex 0 = link partner is not capable of 10base-t half duplex ro 0 5 4:0 selector field link partner selector field ro 00001 reg bit name description read/ write default 515next page 1 = next page requested by link partner 0 = next page not requested ro 0 5 14 acknowledge 1 = link partner acknowledgement 0 = no link partner acknowledgement ro 0 5 13 message page 1 = link partner message page request 0 = no link partner message page request ro 0 5 12 acknowledge 2 1 = link partner can comply next page request 0 = link partner cannot comply next page request ro 0 5 11 toggle link partner toggle ro 0 5 10:0 message field link partner ? s message code ro 0
34 am79c874 preliminary auto-negotiation expansion register (register 6) table 17. auto-negotiation expansion register (register 6) reg bit name description read/ write default 6 15:5 reserved ignore when read. ro 0 64 parallel detection fault 1 = fault detected by parallel detection logic. this fault is due to more than one technology detecting concurrent link up conditions. this bit is cleared upon reading this register. 0 = no fault detected by parallel detection logic. ro/lh 0 63 link partner next page able 1 = link partner supports next page function. 0 = link partner does not support next page function. ro 0 6 2 next page able next page is supported. this bit is permanently tied to 1. ro 1 6 1 page received this bit is set when a new link code word has been received into the auto-negotiation link partner ability register. this bit is cleared upon reading this register. ro/lh 0 60 link partner auto- negotiation able 1 = link partner is auto-negotiation able. 0 = link partner is not auto-negotiation able. ro 0
am79c874 35 preliminary auto-negotiation next page advertisement register (register 7) table 18. auto-negotiation next page advertisement register (register 7) reserved registers (registers 8-15, 20, 22, 25-31) the netphy-1lp device contains reserved registers at addresses 8-15, 20, 22, 25-31. these registers should be ignored when read and should not be written at any time. reg bit name description read/ write default 715np next page indication: 1 = another next page desired. 0 = no other next page transfer desired. rw 0 7 14 reserved ignore when read. ro 0 713mp message page: 1 = message page. 0 = un-formatted page. rw 1 712ack2 acknowledge 2: 1 = will comply with message. 0 = cannot comply with message. rw 0 711tog_tx toggle: 1 = previous value of transmitted link code word equals to 0. 0 = previous value of transmitted link code word equals to 1. rw 0 17 10:0 code message/un-formatted code field. rw 001
36 am79c874 preliminary miscellaneous features register (register 16) table 19. miscellaneous features register (register 16) reg bit name description read/ write default 16 15 repeater 1= repeater mode, full-duplex is inactive, and crs only responds to receive activity. sqe test function is also disabled. rw set by rptr 16 14 intr_levl intr will be active high if this register bit is set to 1. pin requires an external pull-down resistor. intr will be active low if this register bit is set to 0. pin requires an external pull-up resistor. rw 0 16 13:12 reserved write as 0, ignore when read. rw 0 16 11 sqe test inhibit 1 = disable 10base-t sqe testing. 0 = enable 10base-t sqe testing. a col pulse is generated following the completion of a packet transmission . rw 0 16 10 10base-t loopback 1 = enable normal loopback in 10base-t mode. 0 = disable normal loopback in 10base-t mode. rw 1 16 9 gpio_1 data when gpio_1 dir bit is set to 1, this bit reflects the value of the gpio[1] pin. when gpio_1 dir bit is set to 0, the value of this bit will be presented on the gpio[1] pin. rw 0 16 8 gpio_1 dir 1 = gpio[1] pin is an input. 0 = gpio[1] pin is an output. rw 1 16 7 gpio_0 data when gpio_0 dir bit is set to 1, this bit reflects the value of the gpio[0] pin. when gpio[0] dir bit is set to 0, the value of this bit will be presented on the gpio[0] pin. rw 0 16 6 gpio_0 dir 1 = gpio[0] pin is an input. 0 = gpio[0] pin is an output. rw 1 16 5 auto polarity disable 1 = disable auto polarity detection/correction. 0 = enable auto polarity detection/correction. rw 0 16 4 reverse polarity when register 16.5 is set to 0, this bit will be set to 1 if reverse polarity is detected on the media. otherwise, it will be 0. when register 16.5 is set to 1, writing a 1 to this bit will reverse the polarity of the transmitter. note: reverse polarity is detected either through eight inverted nlps or through a burst of an inverted flp. rw 0 16 3:1 reserved write as 0, ignore when read. ro 0 16 0 receive clock control writing a 1 to this bit will shut off rx_clk when incoming data is not present and only if there is link present. rx_clk will resume activity one clock cycle prior to rx_dv going high, and shut off 64 clock cycles after rx_dv goes low. a 0 indicates that rx_clk runs continuously during link whether data is received or not in loopback and pcs bypass modes, writing to this bit does not affect rx_clk. receive clock will be constantly active. rw 0
am79c874 37 preliminary interrupt control/status register (register 17) table 20. interrupt control/status register (register 17) note: * see interrupt source table for bit assignments. diagnostic register (register 18) table 21. diagnostic register (register 18) reg bit name description read/ write default 17 15 jabber_ie jabber interrupt enable rw 0 17 14 rx_er_ie receive error interrupt enable rw 0 17 13 page_rx_ie page received interrupt enable rw 0 17 12 pd_fault_ie parallel detection fault interrupt enable rw 0 17 11 lp_ack_ie link partner acknowledge interrupt enable rw 0 17 10 link_not_ok_ ie link status not ok interrupt enable rw 0 17 9 r_fault_ie remote fault interrupt enable rw 0 17 8 aneg_comp_ie auto-negotiation complete interrupt enable rw 0 17 7 jabber_int this bit is set when a jabber event is detected. rc 0 17 6 rx_er_int this bit is set when rx_er transitions high. rc 0 17 5 page_rx_int this bit is set when a new page is received from link partner during auto-negotiation. rc 0 17 4 pd_fault_int this bit is set for a parallel detection fault. rc 0 17 3 lp_ack_int this bit is set when an flp with the acknowledge bit set is received. rc 0 17 2 link_not_ok int this bit is set when link status switches from ok status to not-ok (fail or ready). rc 0 17 1 r_fault_int this bit is set when a remote fault is detected. rc 0 17 0 a_neg_comp int this bit is set when auto-negotiation is complete. rc 0 reg bit name description read/ write default 18 15:12 reserved ignore when read. ro 0 18 11 dplx 1 = the result of auto-negotiation for duplex is full-duplex. 0 = the result of auto-negotiation for duplex is half-duplex. ro 0 18 10 data rate 1 = the result of auto-negotiation for data-rate arbitration is 100 mbps. 0 = the result of auto-negotiation for data-rate arbitration is 10 mbps. ro 0 18 9 rx_pass operating in 100base-x mode: 1 = a valid signal has been received but the pll has not necessarily locked. 0 = a valid signal has not been received. operating in 10base-t mode: 1 = manchester data has been detected. 0 = manchester data has not been detected. ro 0 18 8 rx_lock 1 = receive pll has locked onto received signal for selected data-rate (10base-t or 100base-x). 0 = receive pll has not locked onto received signal. this bit remains set until it is read. ro/rc 0 18 7:0 reserved ignore when read. ro 0
38 am79c874 preliminary power/loopback register (register 19) table 22. power/loopback register (register 19) reg bit name description read/ write default 19 14:7 reserved rw 00 19 6 tp125 transmit transformer ratio selection: 1 = 1.25:1 0 = 1:1 the default value of this bit is controlled by reset-read value of pin 20. rw 0 19 5 low power mode 1 = enable advanced power saving mode. 0 = disable advanced power saving mode note: under normal operating conditions, this mode should never be disabled. power dissipation will exceed data sheet values, as circuitry for both 10 mbps and 100 mbps will be turned on. rw 1 19 4 test loopback 1 = enable test loopback. data will be transmitted from mii interface to clock recovery and loopback to mii received data. rw 0 19 3 digital loopback 1 = enable loopback. 0 = normal operation. rw 0 19 2 lp_lpbk 1 = enable link pulse loopback. 0 = normal operation. rw 0 19 1 nlp link integrity te s t 1 = in auto-negotiation test mode, send nlp instead of flp in order to test nlp receive integrity. 0 = sending flp in auto-negotiation test mode. rw 0 19 0 reduce timer 1 = reduce time constant for auto-negotiation timer. 0 = normal operation. rw 0
am79c874 39 preliminary mode control register (register 21) table 23. mode control register (register 21) reg bit name description read/ write default 21 15 reserved ro 0 21 14 force_link_10 1 = force link up without checking nlp. forced during local loopback. 0 = normal operation. rw 0 21 13 force_link_100 1 = ignore link in 100base-tx and transmit data. auto- negotiation must be disabled at this time (pin 56 tied low). 0 = normal operation. rw 0 21 12 jabber disable 1 = disable jabber function in phy. 0 = enable jabber function in phy. rw 0 21 11 7_wire_enable 1 = enable 7-wire interface for 10base-t operation. this bit is useful only when the chip is not in pcs bypass mode. 0 = normal operation. rw 0 21 10 conf_aled 1 = activity led only responds to receive operation. 0 = activity led responds to receive and transmit operations for half duplex. led responds to receive activity in full duplex operation. this bit should be ignored when register 0.8 is set to 1 or during repeater mode operation. rw 0 21 9 led_sel 1 = select netphy-1lp device ? s standard led configuration. 0 = use the advanced led configuration. rw set by ledrx / led_sel 21 8 fef_disable 0 = enable far-end-fault generation and detection function. 1 = disable far-end-fault. this bit should be ignored when fx mode is disabled. rw set by tech[2:0], fx_sel , anega pins 21 7 force fef transmit this bit is set to force to transmit far end fault (fef) pattern. rw 0 21 6 rx_er_cnt full when receive error counter is full, this bit will be set to 1. ro/ rc 0 21 5 disable rx_er_cnt 1 = disable receive error counter. 0 = enable receive error counter. rw 0 21 4 dis_wdt 1 = disable the watchdog timer in the decipher. 0 = enable watchdog timer. rw 0 21 3 en_rpbk 1 = enable remote loopback (mdi loopback for 100base-tx). 0 = disable remote loopback. rw 0 21 2 en_scrm 1 = enable data scrambling. 0 = disable data scrambling. when fx mode is selected, this bit will be forced to 0. rw set by scram_en pin 21 1 pcsbp 1 = bypass pcs. 0 = enable pc. rw set by pcsbp pin 21 0 fx_sel 1 = fx mode selected. 0 = disable fx mode. rw set by fx_sel pin
40 am79c874 preliminary disconnect counter register (register 23) table 24. disconnect counter (register 23) receive error counter register (register 24) table 25. receive error counter register (register 24) reg bit name description read/ write default 23 15:0 dlock drop counter count of pll lock drop events rw 0000 reg bit name description read/ write default 24 15:0 rx_er counter count of receive error events rw 0000
am79c874 41 preliminary absolute maximum ratings storage temperature . . . . . . . . . . . . .-55 c to +150 c ambient temperature under bias . . .-55 c to +150 c supply voltage . . . . . . . . . . . . . . . . . . -0.5 v to +5.5 v voltage applied to any input pin. . . . . . . -0.5 v to v dd stresses above those listed under absolute maximum ratings may cause permanent device failure. function- ality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c): operating temperature (ta) . . . . . . . . . 0 c to +70 c supply voltage (all v dd ) . . . . . . . . . . . . . . +3.3 v 5% supply voltage (5-v tolerant pins). . . . . . . +5.0 v 5% industrial (i): operating temperature (ta) . . . . . . . . -40 c to +85 c supply voltage (all v dd ) . . . . . . . . . . . . . . +3.3 v 5% supply voltage (5-v tolerant pins). . . . . . . +5.0 v 5% operating ranges define those limits between which functionality of the device is guaranteed. dc characteristics note: parametric values are the same for commercial and industrial devices. symbol parameter description test conditions minimum maximum units v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 8 ma 0.4 v v oh output high voltage i oh = -4 ma 2.4 v v oll output low voltage (led) i ol (led) = 10 ma 0.4 v v ohl output high voltage (led) i ol (led) = -10 ma v dd ? 0.4 v v cmp input common-mode voltage pecl (note 1) v dd ? 1.5 v dd ? 0.7 v v idiffp differential input voltage pecl (note 1) v dd = maximum 400 1,100 mv v ohp output high voltage pecl (note 4) pecl load v dd ? 1.025 v dd ? 0.60 v v olp output low voltage pecl (note 4) pecl load v dd ? 1.81 v dd ? 1.62 v v sda signal detect assertion threshold p/p (note 2) mlt-3/10base-t test load - 1000 mv v sdd signal detect deassertion threshold p/p (note 3) mlt-3/10base-t test load 200 - mv i il input low current (note 12) v dd = maximum vin = 0.0 v -40 a i ih input high current (note 12) v dd = maximum vin = 2.7 v 40 a v txout differential output voltage (note 5) mlt-3/10base-t test load 950 1050 mv v txos differential output overshoot (note 5) mlt-3/10base-t test load - 0.05 * v txout v v txr differential output voltage ratio (note5 & note 6) mlt-3/10base-t test load 0.98 1.02 -
42 am79c874 preliminary dc characteristics (continued) notes: 1. applies to test1/ fxr+, test0/fxr-, and sdi+ inputs only. valid only when in pecl mode. 2. applies to rx inputs when in mlt-3 mode only. the rx input is guaranteed to assert internal signal detect for any valid peak-to-peak input signal greater than v sda min. 3. applies to rx inputs when in mlt-3 mode only. the rx input is guaranteed to de-assert internal signal for any peak to peak signal less than v sdd max. 4. applies to fxt+ and fxt- outputs only. valid only when in pecl mode. 5. applies to tx differential outputs only. valid only when in the mlt-3 mode. 6. v txr is the ratio of the magnitude of tx in the positive direction to the magnitude of tx in the negative direction. 7. only valid for tx output when in the 10base-t mode. 8. an i oll value applies to led pins. 9. applies to all output pins on the mii port. 10. i oz applies to all high-impedance output pins and all bi-directional pins. for col and crs parameters, i ozh limits are up to 40 a, and iozl up to ? 500 a. 11. 75% activity means 25% ipg and 75% data. 100% activity means minimum ipg. 12. applies to digital inputs and all bidirectional pins. these pins may have internal pull-up or pull-down resistors. rx limits up to 1.0 ma max for i il and ? 1.0 ma for i ih . xtl limits up to 6.0 ma for i il and ? 6.0 ma for i ih . external pull-up/pull-down resistors affect this value. 13. parameter not measured. symbol parameter description test conditions minimum maximum units v tsq rx 10base-t squelch threshold sinusoid 5 mhz am79c874 43 preliminary switching waveforms key to switching waveforms figure 8. mlt-3 receive input must be steady may change from h to l may change from l to h does not apply don ? t care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ? off ? state waveform inputs outputs ks000010-pal v sdd v sda rx 22235i-10
44 am79c874 preliminary figure 9. mlt-3 and 10base-t test load with 1:1 transformer ratio figure 10. mlt-3 and 10base-t test load with 1.25:1 transformer ratio tx+ tx- 0.1 f 75 ? 5% 0.01 f chassis ground 100 ? 2% 1:1 isolation transformer 49.9 ? 49.9 ? v dd 22235i-11 tx+ tx- 0.1 f 75 ? 5% 0.01 f chassis ground 100 ? 2% 1:25:1 isolation transformer 78.1 ? 78.1 ? v dd 22235i-12
am79c874 45 preliminary figure 11. near-end 100base-tx waveform figure 12. 10base-t waveform with 1:1 transformer ratio figure 13. pecl test loads 112 ns v txout v txos tx +v txout -v txout 22235i-13 v tx10ne 0 tx 10base-t 22235i-14 5v 82.5 ? 130 ? pin v dd 69 ? 183 ? pin 22235i-15
46 am79c874 preliminary switching characteristics note: parametric values are the same for commercial devices and industrial devices. system clock signal figure 14. clock signal mlt-3 signals figure 15. mlt-3 test waveform symbol parameter description min. max. unit t clk refclk period 39.998 40.002 ns t clkh refclk width high 18 22 ns t clkl refclk width low 18 22 ns t clr refclk rise time - 5 ns t clf refclk fall time - 5 ns symbol parameter description min. max. unit t txr rise time of mlt-3 signal 3.0 5.0 ns t txf fall time of mlt-3 signal 3.0 5.0 ns t txrfs rise time and fall time symmetry of mlt-3 signal - 5 % t txdcd duty cycle distortion peak to peak - 0.5 ns t txj transmit jitter using scrambled idle signals - 1.4 ns t clr 80% 20% t clf t clkh t clkl t clk refclk 22235i-16 t txr t txf 16 ns tx t xtdcd t xtdcd 1 0 1 0 1 0 1 22235i-17
am79c874 47 preliminary mii management signals figure 16. management bus transmit timing figure 17. management bus receive timing symbol parameter description min. max. unit t mdper mdc period 40 ns t mdwh mdc pulse width high 16 ns t mdwl mdc pulse width low 16 ns t mdpd mdio delay from rising edge of mdc 20 ns t mds mdio setup time to rising edge of mdc 4 ns t mdh mdio hold time from rising edge of mdc 3 ns mdc t mdwh t mdwl t mdper mdio t mdpd mdio_tx.vsd 22235i-18 mdc mdio t mds t mdh 22235i-19
48 am79c874 preliminary mii signals 100 mbps mii transmit timing figure 18. 100 mbps mii transmit start of packet timing symbol parameter description min. max. unit t mts100 tx_er,tx_en, txd[3:0] setup time to tx_clk rising edge 12 - ns t mth100 tx_er, tx_en, txd[3:0] hold time from tx_clk rising edge 0 - ns t mtej100 transmit latency tx_en sampled by tx_clk to first bit of /j/ 60 140 ns t mtecrh100 crs assert from tx_en sampled high - 40 ns t mtecoh100 col assert from tx_en sampled high - 200 ns t mtdcrl100 crs de-assert from tx_en sampled low - 160 ns t mtdcol100 col de-assert from tx_en sampled low 13 240 ns t mtidle100 required de-assertion time between packets 120 - ns t mtp100 tx_clk period 39.998 40.002 ns t mtwh100 tx_clk high 18 22 ns t mtwl100 tx_clk low 18 22 ns tx_clk tx_en t mts100 crs col txd[3:0] tx_er tx t mtwh100 t mtwl100 t mtp100 t mtecrh100 t mtecoh100 t mtej100 t mts100 t mth100 /j/ 22235i-20
am79c874 49 preliminary 100 mbps mii transmit timing (continued) figure 19. 100 mbps transmit end of packet timing tx_clk tx_en t mtidle100 crs col t mtdcrl100 tx /j/ t mtdcol100 /t/ 22235i-21
50 am79c874 preliminary 100 mbps mii receive timing figure 20. 100 mbps mii receive start of packet timing symbol parameter description min. max. unit t mrjcrh100 crs high after first bit of /j/ - 200 ns t mrjcoh100 col high after first bit of /j/ 80 150 ns t mrtcrl100 first bit of /t/ to crs low 130 240 ns t mrtcol100 first bit of /t/ to col low 130 240 ns t mrerl100 first bit of /t/ to rxd[3:0], rx_dv de-asserting (going low) 120 140 ns t mrjra100 first bit of/j/ to rxd[3:0], rx_dv, and rx_en active tbd tbd ns t mrrdc100 rxd[3:0], rx_dv, rx_er valid prior to the rising edge of rx_clk 10 ns t mrcrd100 rxd[3:0], rx_dv, rx_er valid after the rising edge of rx_clk 10 ns rx crs col rx_dv t mrjcoh100 t mrjra100 /j/k/ rx_clk rxd[3:0] rx_er t mrjcrh100 t mrrdc100 t mrcrd100 22235i-22
am79c874 51 preliminary 100 mbps mii receive timing (continued) figure 21. 100 mbps mii receive end of packet timing rx crs col rx_dv t mrtcol100 /t/r/ rx_clk rxd[3:0] rx_er t mrtcrl100 t mrerl100 22235i-23
52 am79c874 preliminary 10 mbps mii transmit timing figure 22. 10 mbps mii transmit start of packet timing symbol parameter description min. max. unit t mts10 tx_en, txd10[3:0] setup time to tx_clk rising edge 12 - ns t mth10 tx_en, txd10[3:0] hold time from tx_clk rising edge 0 - ns t mtep10 transmit latency tx_en sampled by tx_clk to start of packet 240 360 ns t mtecrh10 crs assert from tx_en sampled high - 130 ns t mtecoh10 col assert from tx_en sampled high - 300 ns t mtdcrl10 crs de-assert from tx_en sampled low - 130 ns t mtdcol10 col de-assert from tx_en sampled low - 130 ns t mtidle10 required de-assertion time between packets 300 - ns t mtp10 tx_clk period 399.98 400.02 ns t mtwh10 tx_clk high 180 220 ns t mtwl10 tx_clk low 180 220 ns tx_clk t mts10 tx t mtecrh10 t mteclh10 t mtep10 t mth100 t mts10 tx_en crs col txd[3:0] t mtp10 t mtwh10 t mtwl10 22235i-2 4
am79c874 53 preliminary figure 23. 10 mbps mii transmit end of packet timing tx tx_clk tx_en t mtidle10 crs col t mtdcrl10 t mtdcol10 22235i-25
54 am79c874 preliminary 10 mbps mii receive timing figure 24. 10 mbps mii receive start of packet timing symbol parameter description min. max. unit t mrpcrh10 crs high after start of packet 80 150 ns t mrpcoh10 col high after start of packet 80 150 ns tmrchr10 rxd[3:0], rx_dv, rx_er valid after crs high 100 100 ns t mrrc10 rxd[3:0], rx_dv, rx_er valid prior to the rising of rx_clk10 16 - ns t mrcrd10 rxd[3:0], rx_dv, rx_er valid after the rising edge of rx_clk 12 - ns t mrecrl10 end of packet to crs low 130 190 ns t mrecol10 end of packet to col low 125 185 ns t mrerl10 end of packet to rxd[3:0], rx_dv, rx_er de-asserting (going low) 120 140 ns rx crs col rx_dv rx_clk rxd[3:0] rx_er t mrpcrh10 t mrrc10 t mrcr10 t mrpcoh10 t mrchr10 22235i-26
am79c874 55 preliminary 10 mbps mii receive timing (continued) figure 25. 10 mbps mii receive end of packet timing rx crs col rx_dv rx_clk rxd[3:0] rx_er t mrecrl10 t mrerl10 t mrecol10 22235i-27
56 am79c874 preliminary gpsi signals 10 mbps gpsi receive timing figure 26. gpsi receive timing - start of reception 10 mbps gpsi receive timing figure 27. gpsi receive timing - end of reception (last bit = 0) symbol parameter description min. max. unit t gcd 10crs high to first bit of data 750 850 ns t grcd rising edge of 10rxclk to 10rxd or 10crs 45 55 ns rx bit cell 1 1 bit cell 2 0 bit cell 3 1 bit cell 4 0 bit cell 5 1 10crs 10rxclk 10rxd 10 1 0 1 t gcd t grcd t grcd 22235i-28 symbol parameter description min. max. unit t grcd rising edge of 10rxclk to 10rxd or 10crs 45 55 ns 0 bit n 1 bit (n _ 1) bit (n _ 1) bit n rx 10crs 10rxclk 10rxd t grcd t grcd 22235i-29
am79c874 57 preliminary 10 mbps gpsi receive timing figure 28. gpsi receive timing - end of reception (last bit = 1) 10 mbps gpsi collision timing figure 29. gpsi collision timing symbol parameter description min. max. unit t gdoff delay from rx going to 1 to the rising edge of 10rxclk, which clocks out the last bit of data on 10rxd 190 ns t grcd rising edge of 10rxclk to 10rxd or 10crs 45 55 ns rx 0 bit (n _ 1) 1 bit n bit (n _ 1) bit n 10rxclk 10rxd 10crs t grcd t gdoff 22235i-30 symbol parameter description min. max. unit t gcsclh collision start to 10col high 80 150 ns t gcecll collision end to 10col low 125 185 ns collision presence 10col 0 v + t gcsclh t gcecll 22235i-31
58 am79c874 preliminary 10 mbps gpsi transmit timing figure 30. gpsi transmit timing - start of transmission 10 mbps gpsi transmit timing figure 31. gpsi transmit 10txclk and 10txd timing figure 32. test load for 10rxd, 10crs, 10rxclk, 10txclk and 10col symbol parameter description min. max. unit t gttx delay from the rising edge of the 10txclk which first clocks 10txen high to tx toggling low 240 360 ns 10txclk 10txen tx t gttx 22235i-32 symbol parameter description min. max. unit t gtcdh 10txclk to 10txd or 10txen hold time 20 ns t gdtcs 10txd or 10txen to 10txclk setup time 20 ns t gtch 10txclk width high 45 55 ns t gtcl 10txclk width low 45 55 ns t gtcp 10txclk period 99,995 100,005 ns 10txclk 10txd 10txen t gtcdh t gdtcs t gtcdh t gtcp t gtch t gtcl 22235e-36 50 pf dut 22235e-37
am79c874 59 preliminary physical dimensions pqt80 (measured in millimeters) dwg rev. ae; 8/99 80-lead thin plastic quad flat pack (pqt) pqt80
60 am79c874 preliminary revision summary revisions to other versions this document are as follows: revision c to d 1. corrected reversal of figure 4 and figure 5 in led section. 2. changed ecl to pecl. revision d to e 1. added gpsi timing and diagrams 2. added industrial temperature support revision e to f 1. minor edits revision f to g 1. minor edits revision g to h 1. phyad pins: specified using resistors in the range of 1 k to 4.7 k for setting phyad pins. in gpsi mode, phyad pins must be set to addresses other than 00h. 2. dc characteristics added: v oll and v ohl 3. dc characteristics, added new values for: i il , i ih , i oz. figure 6, advanced led configuration, changes to re- ceive led component changes. revision h to i 1. added clarification to rx_clk throughout document, which is active only while link is established. see pin de- scription for more information. 2. added flow control descriptions to registers 4 and 5 3. register 21, bit 9 was reversed: 1 selects the standard led configuration, while 0 selects the advanced led configuration 4. register 21, bit 2 was changed to indicate en_scrm, scrambler enable; a 1 enables the scrambler. this reg- ister is set by the scram_en pin 5. maximum input voltage is 5.5 v; operating voltage for 5-v tolerant pins is 5.0 v 6. minor edits the contents of this document are provided in connection with advanced micro devices, inc. ( ? amd ? ) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make c hanges to specifi- cations and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or other wise, to any intel- lectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, th e implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's p roduct could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discont inue or make changes to its products at any time without notice. trademarks copyright ? 1999, 2000, 2001 advanced micro devices, inc. all rights reserved. amd, the amd logo and combinations thereof, pcnet-pro and netphy are trademarks of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies.

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